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Machine learning-based defense against process-aware attacks on Industrial Control Systems 基于机器学习的工业控制系统过程感知攻击防御
2016 IEEE International Test Conference (ITC) Pub Date : 2016-07-02 DOI: 10.1109/TEST.2016.7805855
A. Keliris, H. Salehghaffari, Brian R. Cairl, P. Krishnamurthy, M. Maniatakos, F. Khorrami
{"title":"Machine learning-based defense against process-aware attacks on Industrial Control Systems","authors":"A. Keliris, H. Salehghaffari, Brian R. Cairl, P. Krishnamurthy, M. Maniatakos, F. Khorrami","doi":"10.1109/TEST.2016.7805855","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805855","url":null,"abstract":"The modernization of Industrial Control Systems (ICS), primarily targeting increased efficiency and controllability through integration of Information Technologies (IT), introduced the unwanted side effect of extending the ICS cyber-security threat landscape. ICS are facing new security challenges and are exposed to the same vulnerabilities that plague IT, as demonstrated by the increasing number of incidents targeting ICS. Due to the criticality and unique nature of these systems, it is important to devise novel defense mechanisms that incorporate knowledge of the underlying physical model, and can detect attacks in early phases. To this end, we study a benchmark chemical process, and enumerate the various categories of attack vectors and their practical applicability on hardware controllers in a Hardware-In-The-Loop testbed. Leveraging the observed implications of the categorized attacks on the process, as well as the profile of typical disturbances, we follow a data-driven approach to detect anomalies that are early indicators of malicious activity.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122012118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
Built-in self-test for micro-electrode-dot-array digital microfluidic biochips 内置自检微电极点阵列数字微流控生物芯片
2016 IEEE International Test Conference (ITC) Pub Date : 2016-07-02 DOI: 10.1109/TEST.2016.7805847
Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, K. Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee
{"title":"Built-in self-test for micro-electrode-dot-array digital microfluidic biochips","authors":"Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, K. Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee","doi":"10.1109/TEST.2016.7805847","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805847","url":null,"abstract":"A digital microfluidic biochip (DMFB) is an attractive platform for immunoassays, point-of-care clinical diagnostics, DNA sequencing, and other laboratory procedures in biochemistry. However, today's DMFBs suffer from several limitations, including (i) the lack of integrated sensors for real-time detection, (ii) constraints on droplet size and the inability to vary droplet volume in a fine-grained manner, and (iii) the need for special fabrication processes and the associated reliability/yield concerns. To overcome the above limitations, DMFBs based on a micro-electrode-dot-array (MEDA) architecture have been proposed recently. Droplet manipulation on MEDA biochips has also been experimentally demonstrated. In order to ensure robust fluidic operations and high confidence in the outcome of biochemical experiments, MEDA biochips must be adequately tested before they can be used for bioassay execution. We present an efficient built-in self-test (BIST) architecture for MEDA biochips. The proposed BIST architecture can effectively detect defects in a MEDA biochip, and faulty microcells can be identified. Simulation results based on HSPICE and experiments using fabricated MEDA biochips highlight the effectiveness of the proposed BIST architecture.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"2007 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123914418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Output bit selection methodology for test response compaction 测试响应压实的输出位选择方法
2016 IEEE International Test Conference (ITC) Pub Date : 2016-07-02 DOI: 10.1109/TEST.2016.7805873
Wei-Cheng Lien, Kuen-Jong Lee
{"title":"Output bit selection methodology for test response compaction","authors":"Wei-Cheng Lien, Kuen-Jong Lee","doi":"10.1109/TEST.2016.7805873","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805873","url":null,"abstract":"In this paper we propose an output-bit selection technique for test response compaction, with which only a subset of output response bits is selected for observation during testing. Advantages of this technique include zero aliasing, high compaction ratio, full X-tolerance, low area overhead, simple test control and high diagnosability. Also no circuit/ ATPG modification is needed, hence this work can be easily integrated into any typical industrial design/test flow to significantly reduce test cost. Experimental results show that in general less than 10% of test response data of already very compact test sets are needed to detect all testable stuck-at or transition faults, with the reduction ratio increasing with the size of circuits, e.g., only 1.27% of output bits need be observed for b19 that contains more than 1M faults. Efficient test architectures to implement this technique are also presented, which include one that can deal with test responses containing high percentage of unknown values.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129862326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Transformation of multiple fault models to a unified model for ATPG efficiency enhancement 多故障模型转化为ATPG效率提高的统一模型
2016 IEEE International Test Conference (ITC) Pub Date : 2016-07-02 DOI: 10.1109/TEST.2016.7805866
Cheng-Hung Wu, Kuen-Jong Lee
{"title":"Transformation of multiple fault models to a unified model for ATPG efficiency enhancement","authors":"Cheng-Hung Wu, Kuen-Jong Lee","doi":"10.1109/TEST.2016.7805866","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805866","url":null,"abstract":"This paper presents a systematic approach to transform various fault models to a unified model such that all faults of interest can be handled in one ATPG run. The fault models that can be transformed include, but are not limited to, stuck-at faults, various types of bridging faults, and cell-internal faults. The unified model is the aggressor-victim type of bridging fault model. Two transformation methods, namely fault-based and pattern-based transformations, are developed for cell-external and cell-internal faults, respectively. With the proposed approach, one can use an ATPG tool for bridging faults to deal with the test generation problems of multiple fault models simultaneously. Hence the total test generation time can be reduced and highly compact test sets can be obtained. Experimental results show that on average 54.94% (16.45%) and 47.22% (17.51%) test pattern volume reductions are achieved compared to the method that deals with the three fault models separately without (with) fault dropping for ISCAS'89 andIWLS'05 circuits, respectively.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129802521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
An on-chip self-test architecture with test patterns recorded in scan chains 一个片上自测架构，测试模式记录在扫描链中
2016 IEEE International Test Conference (ITC) Pub Date : 2016-07-02 DOI: 10.1109/TEST.2016.7805865
Kuen-Jong Lee, Pin-Hao Tang, M. Kochte
{"title":"An on-chip self-test architecture with test patterns recorded in scan chains","authors":"Kuen-Jong Lee, Pin-Hao Tang, M. Kochte","doi":"10.1109/TEST.2016.7805865","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805865","url":null,"abstract":"This work proposes a novel test architecture that combines the advantages of both scan-based and built-in self-test (BIST) designs. The main idea is to record (store) all required compressed test data in a novel scan chain structure such that the stored data can be extracted, reconstructed and decompressed into required deterministic patterns using an on-chip test controller with a test pattern decompressor. The recording of test data is achieved by modifying the connections between scan cells. Techniques to extract test data from the modified scan cells and to deliver decompressed test patterns to the modified scan cells are presented. The on-chip test controller can automatically generate all required control signals for the whole test procedure. This significantly reduces the requirements on external ATE. Experimental results on OpenSPARC T2, a publicly accessible 8-core processor containing 5.7M gates, show that all required test data for 100% testable stuck-at fault coverage can be stored in the scan chains of the processor with less than 3% total area overhead for the whole test architecture.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114085316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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