2016 IEEE International Test Conference (ITC)最新文献_第5页

Analog fault coverage improvement using final-test dynamic part average testing 利用最终测试动态部件平均测试提高模拟故障覆盖率

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805829

Wim Dobbelaere, Ronny Vanhooren, W. D. Man, K. Matthijs, Anthony Coyette, B. Esen, G. Gielen

引用次数: 18

Mixed-signal ATE technology and its impact on today's electronic system 混合信号ATE技术及其对当今电子系统的影响

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805852

G. Roberts

引用次数: 2

Recycled FPGA detection using exhaustive LUT path delay characterization 使用穷举LUT路径延迟表征的回收FPGA检测

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805854

Md. Mahbub Alam, M. Tehranipoor, Domenic Forte

{"title":"Recycled FPGA detection using exhaustive LUT path delay characterization","authors":"Md. Mahbub Alam, M. Tehranipoor, Domenic Forte","doi":"10.1109/TEST.2016.7805854","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805854","url":null,"abstract":"Field programmable gate arrays (FPGAs) have been extensively used because of their lower non-recurring engineering and design costs, instant availability and reduced visibility of failure, high performance and power benefits. Reports indicate that counterfeit FPGAs are infiltrating the IC supply chain, most of which are recycled type (previously used). Counterfeit components pose a significant threat to the government and industrial sectors of the economy because they undermine the security and reliability of the critical systems and networks. Recycled FPGA detection procedures include parametric test, functional test, and burn-in test that requires golden data and/or parts specifications from original component manufacturers. In this work, a sophisticated ring oscillator design method is used to exploit all the possible paths in look-up tables (LUTs). A recycled FPGA is likely to have fully used, partially used, and unused LUTs. The proposed mapping targets all paths of LUTs and forms a frequency array. A support vector machine is trained with frequency array from unused FPGAs, which differentiates between unused and aged FPGAs. An unsupervised method based on k-means clustering is also proposed to classify recycled components without golden information. Simulation and silicon results demonstrate high rates of success using the proposed methods.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"324 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115844349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays EMACS:用于STT-MRAM阵列测试和表征的高效MBIST架构

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805834

Insik Yoon, Ashwin Chintaluri, A. Raychowdhury

{"title":"EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays","authors":"Insik Yoon, Ashwin Chintaluri, A. Raychowdhury","doi":"10.1109/TEST.2016.7805834","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805834","url":null,"abstract":"Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is an emerging memory technology which exhibits non-volatility, high density, high endurance and nanosecond read and write times. These attributes of STT-MRAM make it suitable for last level embedded caches. However, defect models, faults and test architectures for emerging memory technologies are relatively unexplored. This is further aggravated by the fact that STT-MRAM, like other post-CMOS technologies rely on novel physics of operation, which can result in unexplored read, write and retention fault models. In particular, the stochastic retention failure of STT-MRAM has a large impact on the test time. Conventional test schemes for retention of STT-MRAM need to be redesigned and optimized for testing large STT-MRAM arrays. This paper presents a comprehensive analysis of read, write and retention tests in STT-MRAM arrays. Resistive and capacitive defects and the corresponding faults are studied. A novel MBIST architecture and associated circuits are presented for measuring thermal stability (and hence retention times) in STT-MRAM bits for characterization and manufacturing tests, amidst variations and magnetic coupling. Trade-offs between fault localization, area overhead and test-times are presented.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124216892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning BIST-RM:使用片上时钟扫描和机器学习的bist辅助soc可靠性管理

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805862

Mehdi Sadi, Gustavo K. Contreras, Dat Tran, Jifeng Chen, L. Winemberg, M. Tehranipoor

引用次数: 6

An accurate algorithm for computing mutation coverage in model checking 一种计算模型检验中突变覆盖率的精确算法

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805864

Huina Chao, Huawei Li, Tiancheng Wang, Xiaowei Li, Bo Liu

引用次数: 4

A novel diagnostic test generation methodology and its application in production failure isolation 一种新的诊断测试生成方法及其在生产故障隔离中的应用

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805821

M. E. Amyeen, Dongok Kim, M. Chandrasekar, Mohammad Noman, S. Venkataraman, Anurag Jain, N. Goel, Ramesh Sharma

{"title":"A novel diagnostic test generation methodology and its application in production failure isolation","authors":"M. E. Amyeen, Dongok Kim, M. Chandrasekar, Mohammad Noman, S. Venkataraman, Anurag Jain, N. Goel, Ramesh Sharma","doi":"10.1109/TEST.2016.7805821","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805821","url":null,"abstract":"Faster failure isolation is critical for manufacturing yield ramp and product time to market. Higher diagnosis resolution is essential for faster defect isolation and root-cause identification. A detection oriented test set is targeted for fault coverage and does not provide maximum diagnostic resolution. In this paper, we present the design and architecture of a state of the art diagnostic ATPG tool for industrial-scale designs. We develop a novel diagnostic test generation methodology which first generates deterministic diagnostic test content to distinguish the diagnosis suspects. If tester memory is available then additional N-detect oriented tests are generated to augment the content. Further, we present techniques to improve performance of diagnostic fault simulation for industrial-scale designs. Experimental results on Intel® Core™ microprocessor designs indicate 3X-114X speed up with up-to 2X memory overhead. Silicon failure data collected on sort wafer fails showed the effectiveness of the hybrid diagnostic content in improving the diagnostic resolution by 2.8x to 3X when compared with content generated from an industry standard diagnostic test generator. Silicon results are evaluated on Intel® Core™ microprocessor.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126522319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Pylon: Towards an integrated customizable volume diagnosis infrastructure Pylon:迈向集成的可定制卷诊断基础设施

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805872

Yan Pan, R. Desineni, Kannan Sekar, Atul Chittora, Sherwin Fernandes, Neerja Bawaskar, J. Carulli

引用次数: 0

Effective DC fault models and testing approach for open defects in analog circuits 模拟电路开路缺陷的有效直流故障模型及测试方法

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805830

B. Esen, Anthony Coyette, G. Gielen, Wim Dobbelaere, Ronny Vanhooren

引用次数: 18

Securing digital microfluidic biochips by randomizing checkpoints 通过随机检查点保护数字微流控生物芯片

2016 IEEE International Test Conference (ITC) Pub Date : 2016-07-02 DOI: 10.1109/TEST.2016.7805856

Jack Tang, R. Karri, Mohamed Ibrahim, K. Chakrabarty

引用次数: 9