2016 IEEE International Test Conference (ITC)最新文献_第4页

Low cost ultra-pure sine wave generation with self calibration 低成本超纯正弦波产生与自校准

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805843

Yuming Zhuang, A. K. Unnithan, A. Joseph, Siva Sudani, Benjamin Magstadt, Degang Chen

引用次数: 5

Test point insertion in hybrid test compression/LBIST architectures 在混合测试压缩/LBIST 架构中插入测试点

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805826

Elham K. Moghaddam, N. Mukherjee, J. Rajski, J. Tyszer, Justyna Zawada

{"title":"Test point insertion in hybrid test compression/LBIST architectures","authors":"Elham K. Moghaddam, N. Mukherjee, J. Rajski, J. Tyszer, Justyna Zawada","doi":"10.1109/TEST.2016.7805826","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805826","url":null,"abstract":"Logic built-in self-test (LBIST), originally introduced for board, system, and in-field tests, is now being increasingly used with on-chip test compression. This hybrid approach allows LBIST to become a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs that are targeted for safety-critical and automotive systems. Test points are common in BIST-ready designs where they play a key role in reducing both test application time given a test coverage goal and the overall silicon overhead so that one can get a desired coverage with the minimal number of patterns. Unfortunately, these test points are typically dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG-based test pattern counts cannot guarantee desired random testability. Incompatibility of both types of test points has motivated research presented in this paper. We present a novel hybrid test point technology designed to both reduce deterministic pattern counts and improve fault detection likelihood by means of the same minimal set of test points. Experimental results obtained for large industrial designs illustrate feasibility of the proposed hybrid test points and are reported herein.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128187551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Upper-bound computation for optimal retargeting in IEEE1687 networks IEEE1687网络中最优重定向的上限计算

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805838

Farrokh Ghani Zadegan, Rene Krenz-Baath, E. Larsson

{"title":"Upper-bound computation for optimal retargeting in IEEE1687 networks","authors":"Farrokh Ghani Zadegan, Rene Krenz-Baath, E. Larsson","doi":"10.1109/TEST.2016.7805838","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805838","url":null,"abstract":"IEEE 1687 enables flexible access to on-chip instruments via dynamically reconfigurable networks. Reconfiguration allows reducing instrument access time by keeping only those instruments on the scan-path which are required for each access. To perform reconfiguration and execute commands described in instrument access procedures, scan vectors are generated in a process called retargeting. These vectors are then applied through a number of capture-shift-update (CSU) operations. Generating the optimal set of vectors w.r.t. application time is modeled as an Integer Linear Optimization Problem, which is an NP-hard problem. In the modeling, an IEEE 1687 network is represented as a sequential problem unrolled over a number of time frames, each frame corresponding to a CSU operation. A key challenge is to find the number of required CSU operations, which should be sufficiently high so that the optimal solution is included in the search space but kept as low as possible to keep the model less complex and thus suitable for large IEEE 1687 networks. In this work, we propose a method to compute an upper-bound on the number of required CSU operations. Through experiments, we show that our method results in a tight upper-bound, is applicable to a large variety of IEEE 1687 network designs, and is able to handle large designs.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123095342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Harnessing process variations for optimizing wafer-level probe-test flow 利用工艺变化优化晶圆级探头测试流程

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805835

A. Ahmadi, Constantinos Xanthopoulos, A. Nahar, Bob Orr, M. Pas, Y. Makris

{"title":"Harnessing process variations for optimizing wafer-level probe-test flow","authors":"A. Ahmadi, Constantinos Xanthopoulos, A. Nahar, Bob Orr, M. Pas, Y. Makris","doi":"10.1109/TEST.2016.7805835","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805835","url":null,"abstract":"We propose a methodology for dynamically selecting an optimal probe-test flow which reduces test cost without jeopardizing test quality. The granularity of this decision is at the wafer-level and is made before the wafer reaches the probe station, based on an e-test signature which reflects how process variations have affected this particular wafer. The proposed method offers flexibility by optimizing test flow per process signature and its implementation is simple and compatible with most commonly used Automatic Test Equipment. Furthermore, unlike static test elimination approaches, whose agility is limited by the relative importance of the permanently dropped tests, the proposed method is capable of exploring test cost reduction solutions which achieve very low test escape rates. Decisions are made by an intelligent system which maps every point in the e-test signature space to the most appropriate probe-test flow. Training of the system seeks to optimize the test flow of each process signature in order to maximize test cost reduction for a given target of test escapes, thereby enabling exploration of the trade-off between test cost reduction and test quality. The proposed method is demonstrated on an industrial dataset of a million devices from a 65nm Texas Instruments RF transceiver.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122170589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

RF test accuracy and capacity enhancement on ATE for silicon TV tuners 用于硅电视调谐器的ATE射频测试精度和容量增强

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805842

Y. Fan, A. Verma, Y. Su, L. Rose, J. Janney, V. Do, S. Kumar

引用次数: 0

Fault simulation for analog test coverage 故障模拟模拟测试覆盖

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805831

J. Sequeira, S. Natarajan, P. Goteti, Nitin Chaudhary

引用次数: 5

Automatic test signal generation for mixed-signal integrated circuits using circuit partitioning and interval analysis 利用电路划分和区间分析的混合信号集成电路自动测试信号生成

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805867

Anthony Coyette, B. Esen, Wim Dobbelaere, Ronny Vanhooren, G. Gielen

引用次数: 6

SERDES external loopback test using production parametric-test hardware SERDES外部环回测试使用生产参数测试硬件

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805841

Shalini Arora, Aman Aflaki, Sounil Biswas, Masashi Shimanouchi

{"title":"SERDES external loopback test using production parametric-test hardware","authors":"Shalini Arora, Aman Aflaki, Sounil Biswas, Masashi Shimanouchi","doi":"10.1109/TEST.2016.7805841","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805841","url":null,"abstract":"External loopback testing is an industry standard test for serializer-deserializer (SERDES) interfaces, and it is used to test for at-speed defects in the analog transmission (TX) and reception (RX) buffers. The specific test involves sending pseudorandom bit sequence (PRBS) at high speed from the TX side, looping on the load-board and receiving on the RX side where the sequence is checked to calculate bit error rate (BER). To achieve parametric coverage on the buffers, it is required to have tester access at the SERDES pins. However, the on-board component populated for this tester access may lead to poor channel insertion and return loss due to reflections from these additional components. This, in turn, may lead to unacceptable BER at higher data rates. Consequently, it is a common practice to use one type of load-board for parametric/DC testing and another type for AC/at-speed testing. This paper describes a dedicated production load-board that is designed to achieve tester access on the SERDES pins using a resistor network. Using this load-board, external loopback could be operated successfully up to 20Gbps without sacrificing parametric test capability.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131083202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Statistical outlier screening as a test solution health monitor 统计离群值筛选作为测试解决方案运行状况监控器

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805837

David Shaw, Dirk Hoops, K. Butler, A. Nahar

引用次数: 6

Variation and failure characterization through pattern classification of test data from multiple test stages 通过从多个测试阶段的测试数据模式分类的变化和失效表征

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805845

Chun-Kai Hsu, Peter Sarson, G. Schatzberger, F. Leisenberger, J. Carulli, Siddhartha Siddhartha, K. Cheng

引用次数: 5