2016 IEEE International Test Conference (ITC)最新文献_第3页

Putting wasted clock cycles to use: Enhancing fortuitous cell-aware fault detection with scan shift capture 利用浪费的时钟周期:通过扫描移位捕获增强偶然的单元感知故障检测

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805828

Fanchen Zhang, D. Hwong, Yi Sun, Allison Garcia, Soha Alhelaly, G. Shofner, L. Winemberg, Jennifer Dworak

{"title":"Putting wasted clock cycles to use: Enhancing fortuitous cell-aware fault detection with scan shift capture","authors":"Fanchen Zhang, D. Hwong, Yi Sun, Allison Garcia, Soha Alhelaly, G. Shofner, L. Winemberg, Jennifer Dworak","doi":"10.1109/TEST.2016.7805828","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805828","url":null,"abstract":"Probabilistic approaches to the detection of untargeted defects, such as n-detect and standard LBIST (logic built-in-self-test), generally suffer from the need to apply very long test sets to achieve good coverage. However, more targeted approaches that attempt to explicitly model new types of defects, such as cell-aware faults, so that they can be deterministically detected may also lead to unacceptably long test sets. Generally, when tests are applied to circuits that contain scan chains, test results are only captured once the entire pattern has been shifted in and the desired deterministic pattern has been applied. Intervening shift cycles serve only as overhead. This is done because capturing data in the circuit's scan flip-flops during scan shift would destroy the pattern being shifted in. However, if data is captured in shadow flops in a MISR instead, those shift cycles could be used to obtain additional fault coverage. In this paper, we investigate the ability of the intervening shift cycles to achieve high static cell-aware fault coverage using only the test patterns generated to detect stuck-at faults. We also investigate reducing the number of shadow flops required. Our results show that high cell-aware coverage is achievable even when only a stuck-at test set is applied - in some cases equal to the coverage obtained by a dedicated cell-aware test set.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116676607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Accessing 1687 systems using arbitrary protocols 使用任意协议访问1687系统

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805839

M. Portolan

引用次数: 3

Supply-voltage optimization to account for process variations in high-volume manufacturing testing 电源电压优化，以说明在大批量生产测试过程的变化

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805846

Gurunath Kadam, M. Rudack, K. Chakrabarty, Juergen Alt

{"title":"Supply-voltage optimization to account for process variations in high-volume manufacturing testing","authors":"Gurunath Kadam, M. Rudack, K. Chakrabarty, Juergen Alt","doi":"10.1109/TEST.2016.7805846","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805846","url":null,"abstract":"In a high-volume manufacturing environment, it is difficult to set up test conditions, including supply-voltage levels, that can take into account the wide range of interdie process variations on a wafer. Test conditions that do not take into consideration these process variations can lead to either yield loss or poor quality control. In this work, we propose a method to identify supply-voltage levels to test semiconductor chips based on the process variations experienced by them, while also adapting these supply-voltage levels based on the chip locations on the wafer. For this purpose, we first identified various process zones on the wafer, based on frequencies of on-chip ring oscillators. Next we modeled the ring oscillator (RO) performance in terms of the variations in SPICE parameters using the design of experiments (DoE) method. The equation corresponding to the DoE model was solved for each process zone on the wafer in order to fit a set of independent SPICE parameters set for the corresponding zone. These independent SPICE parameters were then used to create an updated SPICE model for the ring oscillator corresponding to each zone, and these SPICE models were used to derive an appropriate supply-voltage level for each zone. The results were used to test 250 devices to identify chips that exhibit significant performance deviation compared to other chips from the same zone. Among these 250 devices, 89 belonged to the slow zone, 87 belonged to the medium-fast zone, and 74 belonged to the fast process zone. A total of seven devices from the medium-fast zone and nine devices from the fast zone showed performance deviations and they were successfully screened.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127633689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Memory repair for high fault rates 内存修复高故障率

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805874

P. Papavramidou

引用次数: 3

Using symbolic canceling to improve diagnosis from compacted response 利用符号消去改进压缩响应的诊断

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805823

Kamran Saleem, N. Touba

{"title":"Using symbolic canceling to improve diagnosis from compacted response","authors":"Kamran Saleem, N. Touba","doi":"10.1109/TEST.2016.7805823","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805823","url":null,"abstract":"This paper addresses the problem of performing diagnosis using production test results in a test compression environment. For linear response compactors, such as multiple-input shift register (MISRs), diagnosis must be performed from signatures. The key idea in this work is to use symbolic canceling in MISR signatures to extract information from both the MISR signature bits with errors as well as those that are error-free to provide more precise diagnostic information. A fundamentally new technique for precisely identifying error locations for propagation cones reaching fewer scan cells than the size of the MISR is described. The proposed approach does not require any additional hardware or extra data to be collected. It uses off-line software-based processing (symbolic simulation combined with Gaussian elimination) to extract information from signatures to deduce error locations even when there are a large number of errors. Unlike existing techniques for diagnosis from signatures, the proposed diagnosis approach can be used even when there are unknown (X) values in the output response. Experimental results demonstrate the reductions in suspect set size that can be obtained with the proposed techniques.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127493686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Test time efficient group delay filter characterization technique using a discrete chirped excitation signal 测试使用离散啁啾激励信号的时间高效群延迟滤波器表征技术

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805853

Peter Sarson

引用次数: 3

Handling wrong mapping: A new direction towards better diagnosis with low pin convolution compressors 处理错误映射:低引脚卷积压缩器更好诊断的新方向

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805822

Subhadip Kundu, Parthajit Bhattacharya, R. Kapur

引用次数: 0

Test chip design for optimal cell-aware diagnosability 测试芯片设计的最佳细胞感知诊断能力

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805850

Soumya Mittal, Z. Liu, Ben Niewenhuis, R. D. Blanton

引用次数: 8

I-Q signal generation techniques for communication IC testing and ATE systems 用于通信IC测试和ATE系统的I-Q信号生成技术

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805858

Masahiro Murakami, Haruo Kobayashi, S. N. Mohyar, O. Kobayashi, T. Miki, Junya Kojima

引用次数: 20

Active reliability monitor: Defect level extrinsic reliability monitoring on 22nm POWER8 and zSeries processors 主动可靠性监测:对22nm POWER8和zSeries处理器进行缺陷级外部可靠性监测

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805871

Michael Johnson, Brian D. Noble, Mark Johnson, James Crafts, C. Manya, John Deforge

{"title":"Active reliability monitor: Defect level extrinsic reliability monitoring on 22nm POWER8 and zSeries processors","authors":"Michael Johnson, Brian D. Noble, Mark Johnson, James Crafts, C. Manya, John Deforge","doi":"10.1109/TEST.2016.7805871","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805871","url":null,"abstract":"Monitoring extrinsic reliability performance in a given technology is often performed in a passive manner. Semiconductor devices (die) are sampled out of production environment, subjected to a series of electrical and mechanical stresses, and finally tested extensively to determine if stressing produced additional fails. This strategy is prone to missing issues which are localized to a lots or wafers and is not likely to identify potential field reliability problems early enough to remove samples prior to shipment to the customer. We have created a system which continuously scans memory array repairs (correctable errors) across multiple test steps including Burn In and Voltage Screen, applies a pattern classification algorithm, and enables reliability information to be collected for every die. We will show that monitoring extrinsic defects at Wafer Final Test and through Burn In on every die for every product in a technology is crucial to a robust technology reliability strategy. Additionally we demonstrate a low cost high efficiency system, the Active Reliability Monitor, which accomplishes that goal using 22nm POWER8 and zSeries processor data. The system is shown to provide similar quality data to traditional reliability screening methods while also allowing for automated real time reaction to reliability indicators, specific-defect-type monitoring, and robust monitoring across products in the technology. The tool has enabled the identification of new screen procedures used for the containment of several problematic lots and rapid evaluation of the reliability degradation for any suspect reliability vintages.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127676330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2