2016 IEEE International Test Conference (ITC)最新文献_第2页

A built-in self-repair scheme for DRAMs with spare rows, columns, and bits 具有备用行、列和位的dram的内置自我修复方案

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805832

Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, D. Kwai, Yung-Fa Chou

引用次数: 13

Defect tolerance for CNFET-based SRAMs 基于cnfet的sram的缺陷容忍度

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805833

Tianjian Li, Li Jiang, Xiaoyao Liang, Q. Xu, K. Chakrabarty

引用次数: 1

Cross-layer system reliability assessment framework for hardware faults 硬件故障跨层系统可靠性评估框架

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805863

Alessandro Vallero, A. Savino, G. Politano, S. Carlo, Athanasios Chatzidimitriou, Sotiris Tselonis, Manolis Kaliorakis, D. Gizopoulos, Marc Riera, R. Canal, Antonio González, Maha Kooli, A. Bosio, G. D. Natale

{"title":"Cross-layer system reliability assessment framework for hardware faults","authors":"Alessandro Vallero, A. Savino, G. Politano, S. Carlo, Athanasios Chatzidimitriou, Sotiris Tselonis, Manolis Kaliorakis, D. Gizopoulos, Marc Riera, R. Canal, Antonio González, Maha Kooli, A. Bosio, G. D. Natale","doi":"10.1109/TEST.2016.7805863","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805863","url":null,"abstract":"System reliability estimation during early design phases facilitates informed decisions for the integration of effective protection mechanisms against different classes of hardware faults. When not all system abstraction layers (technology, circuit, microarchitecture, software) are factored in such an estimation model, the delivered reliability reports must be excessively pessimistic and thus lead to unacceptably expensive, over-designed systems. We propose a scalable, cross-layer methodology and supporting suite of tools for accurate but fast estimations of computing systems reliability. The backbone of the methodology is a component-based Bayesian model, which effectively calculates system reliability based on the masking probabilities of individual hardware and software components considering their complex interactions. Our detailed experimental evaluation for different technologies, microarchitectures, and benchmarks demonstrates that the proposed model delivers very accurate reliability estimations (FIT rates) compared to statistically significant but slow fault injection campaigns at the microarchitecture level.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134613205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

Accurate anomaly detection using correlation-based time-series analysis in a core router system 基于相关时间序列分析的核心路由器系统精确异常检测

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805836

Shi Jin, Zhaobo Zhang, K. Chakrabarty, Xinli Gu

{"title":"Accurate anomaly detection using correlation-based time-series analysis in a core router system","authors":"Shi Jin, Zhaobo Zhang, K. Chakrabarty, Xinli Gu","doi":"10.1109/TEST.2016.7805836","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805836","url":null,"abstract":"Fault tolerance is used in communication systems to ensure high reliability and rapid error recovery. The effectiveness of most proactive fault-tolerant mechanism depends on whether anomalies can be accurately detected before a failure occurs. However, traditional anomaly detection techniques fail to detect “outliers” when the monitored data involves temporal measurements and exhibits significantly different statistical characteristics for its constituent features. We describe the design of an anomaly detector that monitors the time-series data of a complex core router system. Anomaly detection techniques are compared in terms of their effectiveness for detecting different types of anomalies. A feature-categorizing-based hybrid method is proposed to overcome the difficulty of detecting anomalies in features with different statistical characteristics. Furthermore, a correlation analyzer is implemented to remove irrelevant and redundant features. Three types of synthetic anomalies, generated using a small amount of real data for a commercial telecom system, are used to validate the proposed anomaly detector.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125592676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Minimal area test points for deterministic patterns 确定模式的最小面积测试点

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805825

Yingdi Liu, Elham K. Moghaddam, N. Mukherjee, S. Reddy, J. Rajski, J. Tyszer

引用次数: 5

Diagnostic resolution improvement through learning-guided physical failure analysis 通过学习引导物理故障分析提高诊断分辨率

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805824

Carlston Lim, Yang Xue, Xin Li, R. D. Blanton, M. E. Amyeen

{"title":"Diagnostic resolution improvement through learning-guided physical failure analysis","authors":"Carlston Lim, Yang Xue, Xin Li, R. D. Blanton, M. E. Amyeen","doi":"10.1109/TEST.2016.7805824","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805824","url":null,"abstract":"An accurate and high-resolution diagnosis enables physical failure analysis (PFA) to identify and understand the root-cause of integrated-circuit failure. Despite many existing techniques for improving diagnosis, resolution is still far from ideal, which hinders PFA and other analyses. To address this challenge, we extend the capability of PADRE (physically-aware diagnostic resolution enhancement), a powerful machine learning based diagnosis resolution improvement technique, with a novel, active learning (AL) based PFA selection approach. An active-learning based PADRE (AL PADRE) selects the most useful defects for PFA in order to improve diagnostic resolution. AL PADRE provides an alternative to the normal PFA selection procedure, it improves the the accuracy of PADRE, and thus enables a more accurately improved resolution. AL PADRE is validated by both simulation-based experiment and silicon experiment. Simulation-based experiments show that by using AL PADRE, the number of PFAs required for increasing the accuracy to a stable level of 90% is reduced by more than 60% on average compared to baseline approach, and AL PADRE consistently outperforms the baseline approach for accuracy improvement in various scenarios. In the silicon experiment, by using AL PADRE, the number of chips needed to undergo PFA was reduced by more than 6x in order to increase diagnosis accuracy by more than 20%.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122020390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Automated measurement of defect tolerance in mixed-signal ICs 混合信号集成电路缺陷容差的自动测量

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805869

S. Sunter, Alessandro Valerio, Riccardo Miglierina

引用次数: 0

A suite of IEEE 1687 benchmark networks 一套IEEE 1687基准网络

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805840

A. Tsertov, A. Jutman, S. Devadze, M. Reorda, E. Larsson, Farrokh Ghani Zadegan, R. Cantoro, Mehrdad Montazeri, Rene Krenz-Baath

{"title":"A suite of IEEE 1687 benchmark networks","authors":"A. Tsertov, A. Jutman, S. Devadze, M. Reorda, E. Larsson, Farrokh Ghani Zadegan, R. Cantoro, Mehrdad Montazeri, Rene Krenz-Baath","doi":"10.1109/TEST.2016.7805840","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805840","url":null,"abstract":"The saturation of the IJTAG concept and its approval as the IEEE 1687 standard in 2014 has generated a wave of research activities and created demand for a set of appropriate and challenging benchmarks. This paper presents such a set developed by an industrial and academic consortium and constructed in a way that facilitates objective comparison of experimental results across research groups as well as represents challenging network examples exhaustively utilizing features and constructs defined by the standard. The suite is arranged in four comprehensive categories, each having its particular purpose and composition principles, as described in the paper. We have also made an analysis of limitations of previous popular and ad-hoc benchmark sets as these limitations majorly motivated our current action. The new public-domain benchmarks are distributed together with source files and documentation through the dedicated web site. Some of the previous research results on IEEE 1687 have been reapplied on the new benchmarks set, thus creating an important initial reference point for the research community.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128206792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 42

What we know after twelve years developing and deploying test data analytics solutions 经过12年开发和部署测试数据分析解决方案，我们知道了什么

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805844

K. Butler, A. Nahar, W. R. Daasch

引用次数: 10

DE-LOC: Design validation and debugging under limited observation and control, pre- and post-silicon for mixed-signal systems DE-LOC:混合信号系统在有限观察和控制下的设计验证和调试，前置和后硅

2016 IEEE International Test Conference (ITC) Pub Date : 2016-11-01 DOI: 10.1109/TEST.2016.7805868

B. Muldrey, Sabyasachi Deyati, A. Chatterjee

{"title":"DE-LOC: Design validation and debugging under limited observation and control, pre- and post-silicon for mixed-signal systems","authors":"B. Muldrey, Sabyasachi Deyati, A. Chatterjee","doi":"10.1109/TEST.2016.7805868","DOIUrl":"https://doi.org/10.1109/TEST.2016.7805868","url":null,"abstract":"In the modern mixed-signal SoC design cycle, designers are frequently tasked with detecting and diagnosing behavioral discrepancies between design descriptions given at different levels of hierarchy, e.g. behavioral vs. transistor level descriptions or behavioral/transistor level descriptions vs. fabricated silicon. One problem is detection, to determine if behavioral differences between design descriptions exist. If such differences (anomalies) are detected, then diagnosis is concerned with identifying the module in a hierarchical design description of the system that is most likely the root cause of the anomaly (typically under the constraint that only the primary outputs of the top-level hierarchies are observed. Previously proposed machine-learning classifiers require prior knowledge about the kinds of likely design errors typically encountered. In this work, we present a novel technique for the algorithmic foundation of circuit diagnosis predictions which does not require any assumptions about the nature of design errors. Our method employs iterative and alternate on-the-fly test generation and least-squares fitting of embedded low-order nonlinear filters to produce a best-guess estimate of the root cause of the anomaly. Experiments are conducted on two test vehicles, an RF transceiver and a phase-locked loop, several bug models are implemented, and the system's diagnosis predictions are analyzed.","PeriodicalId":210661,"journal":{"name":"2016 IEEE International Test Conference (ITC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129551632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2