A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath

Abstract

Stringent test-time and yield targets together with increased embedded memory content has resulted in increased power and area of memory self-test and repair logic. It is common for high performance IP cores (CPU/DSP/GPU/etc.) to have embedded BIST datapath (DP) that is shared with functional logic to minimize the IP BIST area overhead and ease IP design-closure. However, different IP cores (from same/different vendors) have diverse embedded BIST DP implementations. While having a dedicated memory self-test and repair controller for each IP simplifies design implementation, it is area and power intensive. In this paper, we propose a reconfigurable centralized memory built-in self-repair (BISR) architecture that supports multiple IPs with diverse embedded BIST DP implementations while being area efficient. We also present a power and timing-aware BISR synthesis flow that enables test time reduction while satisfying timing and power constraints. Experimental results on 28nm designs indicate about 2.4X area reduction compared to native EDA solution. The proposed solution also helps achieve 4.9X reduction in test time.