Advanced test methodology for complex SoCs

Abstract

This paper presents the latest test methodology for NVIDIA's multi-billion transistor Mobile System on Chip (SoC) and Graphics Processing Unit (GPU). The paper describes the innovations that enhance the SoC plug-n-play scheme in terms of DFT. It also demonstrates how the architecture enables ultra-low pin count testing together with test data reuse and efficient test scheduling to improve the test quality while lowering the test cost. We present a scalable scan interface methodology coupled with core isolation and advanced clocking design while keeping the overall power budget for test within the limits of SoC Thermal Design Power (TDP). Silicon results are shared to demonstrate the effectiveness of this architecture.