Logic characterization vehicle design reflection via layout rewiring

Abstract

Continued scaling of semiconductor fabrication processes has made achieving yield targets increasingly difficult. The design and fabrication of various types of test vehicles is one approach for enabling fast yield learning. Recent work introduced the Carnegie Mellon logic characterization vehicle (CM-LCV). The CM-LCV design methodology uses regularity and existing testability theory to produce logic-based designs that are both highly testable and diagnosable. For the CM-LCV to be effective for yield learning, it must reflect the design characteristics of actual product layouts. Previous work enables incorporation of a standard-cell distribution derived from product designs into an LCV while simultaneously ensuring optimal testability. In this work, a new method is proposed for constructing a CM-LCV that reflects the design characteristics of a product through rewiring either the entire layout or some portion thereof. Four different approaches for rewiring are examined, and the results of each approach are evaluated using a variety of metrics. Experiment results reveal that a product layout can be easily rewired to construct an LCV with reasonable wirelength with reasonable CPU time. Rewiring has many advantages including the transformation of an actual product front-end to a logic-based test chip that has significant transparency to failure. Consequently, this means that front-end masks from an actual product can be re-used to create an effective LCV that is both more reflective and inexpensive to fabricate.