{"title":"Development and industrialisation","authors":"M. Riffiod, P. Caspi, C. Piala, J. Voirin","doi":"10.1145/1266366.1266672","DOIUrl":"https://doi.org/10.1145/1266366.1266672","url":null,"abstract":"This second technical session illustrates the methodological dimensions of technology transfer. It elaborates on some methodologies deployed in critical steps of the whole embedded systems development process, particularly to specify safety critical embedded systems, to manage obsolescence of components and to certify the airworthiness of the final solutions.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128525019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Interactive presentation: Process tolerant β-ratio modulation for ultra-dynamic voltage scaling","authors":"Myeong-Eun Hwang, T. Cakici, Kaushik Roy","doi":"10.1145/1266366.1266705","DOIUrl":"https://doi.org/10.1145/1266366.1266705","url":null,"abstract":"Most wireless and hand-held gadgets work in burst mode, and the performance demand varies with time. When the performance requirement is low, the supply voltage can be dithered and the circuit can enter from superthreshold region to subthreshold region (Vdd < VT). Such ultra dynamic voltage scaling (UDVS), where the supply voltage switches from 1.2V to 200mV (say), enables remarkable decrease in power consumption with \"acceptable\" performance penalty in the non-burst mode of operation. However, subthreshold operation is very sensitive to process variation (PV) due to the reduced noise margin, and may not work properly unless corrective measures are taken. In this paper, we model the trip voltage in both subthreshold and superthreshold regions, and analyze the impact of PV in UDVS. We also propose a circuit design technique such that the same logic gate can efficiently operate in both superthreshold and subthreshold regions under PV. We do that by modulating the β-ratio (P-to-N ratio) of the logic gates. By proper β-ratio modulation, we show that the proposed methodologies can lower energy dissipation per cycle by more than an order of magnitude (42X) in non-burst mode with reduced impact to PVs.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129410617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Wittmann, M. Vanzi, H.-J. Wassener, N. Nandra, J. Kunkel, J. Franca, C. Münker
{"title":"Life begins at 65: unless you are mixed signal?","authors":"R. Wittmann, M. Vanzi, H.-J. Wassener, N. Nandra, J. Kunkel, J. Franca, C. Münker","doi":"10.1109/DATE.2007.364413","DOIUrl":"https://doi.org/10.1109/DATE.2007.364413","url":null,"abstract":"The old school of analog designers, exemplified by pioneer Bob Pease, is becoming an extinct species. But the demand for analog/mixed-signal IP blocks has never been greater, especially at 65 nm and below. Can this demand be met by using externally designed 3rd party analog/mixed-signal IP? Or is the implementation of revolutionary changes to traditional work flows and analog design processes a suitable option? Which solutions that help in increasing design efficiency are currently on the table? In the future, which side of the table will analog designers of Bob Pease's generation sit: the IP provider or the chip company? Or are their skills redundant for the 65 nm analog design challenges?","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121372540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Casale-Rossi, A. Strojwas, R. Aitken, A. Domic, C. Guardiani, P. Magarshack, D. Pattullo, Joseph Sawicki
{"title":"DFM/DFY: should you trust the surgeon or the family doctor?","authors":"M. Casale-Rossi, A. Strojwas, R. Aitken, A. Domic, C. Guardiani, P. Magarshack, D. Pattullo, Joseph Sawicki","doi":"10.1109/DATE.2007.364631","DOIUrl":"https://doi.org/10.1109/DATE.2007.364631","url":null,"abstract":"Everybody agrees that curing DFM/DFY issues is of paramount importance at 65 nanometers and beyond. Unfortunately, there is disagreement about how and when to cure them. \"Surgeons\" suggest a GDSII-centered approach, potentially invasive, while \"family doctors\" recommend a more pervasive approach, starting from RTL. As in real life, \"surgery\" and \"medicine\" represent two different schools of thought in the DFM/DFY arena. Both involve risks.\u0000 This panel will examine these two approaches from high-level design all the way to manufacturing. We have assembled a set of panelists that represent a broad cross-section of semiconductor industry. Although there is general agreement among the panelists that both approaches are necessary and that prevention is the best way to proceed, they also acknowledge that the surgery may be unavoidable in such \"hazardous\" conditions as state-of-the-art technologies.\u0000 However, as always, \"the devil is in the details,\" and the diverse approaches to DFM presented below should make this panel quite interesting. We are also counting on the feedback from the IC design community to assess if these approaches are sufficient and practical enough to deal with the \"health hazards.\" We are looking forward to an exciting discussion that will challenge our esteemed panelists.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115491531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Interactive presentation: Time-constrained clustering for DSE of clustered VLIW-ASP","authors":"Mario Schölzel","doi":"10.1145/1266366.1266465","DOIUrl":"https://doi.org/10.1145/1266366.1266465","url":null,"abstract":"In this paper we describe a new time-constrained clustering algorithm. It is coupled with a time-constrained scheduling algorithm and used for Design-Space-Exploration (DSE) of clustered VLIW processors with heterogeneous clusters and heterogeneous functional units. The algorithm enables us to reduce the complexity of the DSE, because the parameters of the VLIW are derived from the clustered schedule of the considered application which is produced during a single compilation step. Several compilations of the same application with different VLIW-parameter settings are not necessary. Our proposed algorithm is integrated into a DSE-Tool in order to explore the best parameters of a clustered VLIW processor for several basic blocks of signal processing applications. The obtained results are compared to the results of Lapinskii's work and show, that, for most benchmarks, we are able to save ports in the register file of each cluster.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124859666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Sathanur, A. Calimera, Luca Benini, A. Macii, Enrico Macii, M. Poncino
{"title":"Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing","authors":"A. Sathanur, A. Calimera, Luca Benini, A. Macii, Enrico Macii, M. Poncino","doi":"10.1145/1266366.1266704","DOIUrl":"https://doi.org/10.1145/1266366.1266704","url":null,"abstract":"A molding press for insert molding of composite articles. The press has upper and lower plates movable between open and closed positions, and a die set positioned between the plates. The die set includes a core member with surfaces defining a portion of the molding cavity and another surface for receiving and supporting the insert. The core member also includes means defining a part of an area for receiving a charge of curable material and a part of a scrap forming cavity. A second mold member has surfaces defining a second portion of the article forming cavity and a second portion of said strap forming cavity, and the second mold member also includes means for engaging the insert and cooperating with it to form an axially movable flash barrier. The second mold part also has means cooperating with the insert to form a second, stationary flash barrier on an angularly related surface of the insert. The third mold member is adapted to reciprocate relative to the first and second members and has one surface for engaging a portion of said charge of moldable material for moving it from the receiving area through the scrap forming area and into the molding cavity. The first and third elements also include surfaces lying opposite each other in the closed position of said mold which serve to define a slightly spaced apart, substantially circumferentially continuous passage of reduced cross-section which separates scrap forming area from the article forming cavity. The second and third mold members are resiliently urged, in the closed position of the mold towards the first member by separate sets of resilient means interposed between portions of the second and third members and portions of the top mold plate. The method includes establishing a movable flash barrier by engaging an axial insert surface during mold closure. A seal with a unitary body, having two or more lips and a deep axial cross-section, is also described.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123832627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Zjajo, Manuel J. Barragan Asian, J. P. D. Gyvez
{"title":"Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits","authors":"A. Zjajo, Manuel J. Barragan Asian, J. P. D. Gyvez","doi":"10.1145/1266366.1266650","DOIUrl":"https://doi.org/10.1145/1266366.1266650","url":null,"abstract":"This paper reports a new built-in self-test scheme for analog and mixed-signal devices based on die-level process monitoring. The objective of this test is not to replace traditional specification-based tests, but to provide a reliable method for early identification of excessive process parameter variations in production tests that allows quickly discarding of the faulty circuits. Additionally, the possibility of on-chip process deviation monitoring provides valuable information, which is used to guide the test and to allow the estimation of selected performance figures. The information obtained through guiding and monitoring process variations is re-used and supplement the circuit calibration.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114674867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Aycinena, Eric Bantegnie, Gerard Ladier, Ralph Mueller, F. Gasperoni, Alex Wilson
{"title":"Towards total open source in aeronautics and space?","authors":"P. Aycinena, Eric Bantegnie, Gerard Ladier, Ralph Mueller, F. Gasperoni, Alex Wilson","doi":"10.1145/1266366.1266707","DOIUrl":"https://doi.org/10.1145/1266366.1266707","url":null,"abstract":"Aeronautics and space are extraordinarily technical fields of engineering and science that reside within a niche characterized by unique end-product requirements. The severe operating conditions in flight or in space, in combination with the need for mission-critical reliability, create a difficult and challenging level of expectation for those who develop the hardware and software that goes into systems for aeronautics and space.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117015957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures","authors":"P. S. B. Nascimento, M. Lima","doi":"10.1109/DATE.2006.243761","DOIUrl":"https://doi.org/10.1109/DATE.2006.243761","url":null,"abstract":"Temporal partitioning techniques are useful to implement large and complex applications, which can be split into partitions in FPGA devices. In order to minimize resources, each of these partitions can be multiplexed in an only FPGA area by reconfiguration techniques. These multiplexing approaches increase the effective area, allowing parallelism exploitation in small devices. However, multiplexing means reconfiguration time, which can cause impact on the application performance. Thus, intensive parallelism exploitation in massive computation applications must be explored to compensate such inconvenient and improve processes. In this work, a temporal partitioning technique is presented for a class of image processing (massive computation) applications. The proposal technique is based on the algorithmic complexity (area x time) for each task that composes the applications. Experimental results are used to demonstrate the efficiency of the approach when compared to the optimal solution obtained by exhaustive timing search.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114316654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Marculescu, J. Rabaey, A. Sangiovanni-Vincentelli
{"title":"Is \"Network\" the next \"Big Idea\" in design?","authors":"R. Marculescu, J. Rabaey, A. Sangiovanni-Vincentelli","doi":"10.1109/DATE.2006.244112","DOIUrl":"https://doi.org/10.1109/DATE.2006.244112","url":null,"abstract":"As the complexity of nowadays systems continues to grow, we are moving away from creating individual components from scratch, toward methodologies that emphasize composition of re-usable components via the network paradigm. Complex component interactions can create a range of amazing behaviors, some useful, some unwanted, some even dangerous. To manage them, a “science” for network design is evolving, applicable in some surprising areas. In this paper, we consider a few application domains and discus the design challenges involved from a methodology standpoint. From large-scale hardware/software systems, to dynamically adaptive sensor networks, and network-on-chip architectures, these ideas find wide application.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125545757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}