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Exploring "temperature-aware" design in low-power MPSoCs 探索低功耗mpsoc的“温度感知”设计
Design, Automation and Test in Europe Pub Date : 2006-03-06 DOI: 10.1109/DATE.2006.243741
Giacomo Paci, P. Marchal, Francesco Poletti, L. Benini
{"title":"Exploring \"temperature-aware\" design in low-power MPSoCs","authors":"Giacomo Paci, P. Marchal, Francesco Poletti, L. Benini","doi":"10.1109/DATE.2006.243741","DOIUrl":"https://doi.org/10.1109/DATE.2006.243741","url":null,"abstract":"The power density inside high performance systems continues to rise with every process technology generation, thereby increasing the operating temperature and creating “hot spots” on the die. As a result, the performance, reliability and power consumption of the system degrade. To avoid these “hot spots”, “temperature-aware” design has become a must. For low-power embedded systems though, it is not clear whether similar thermal problems occur. These systems have very different characteristics from the high performance ones: they consume hundred times less power, they are based on a multi-processor architecture with lots of embedded memory and rely on cheap packaging solutions. In this paper, we investigate the need for temperature-aware design in a low-power systems-on-a-chip and provide guidlines to delimit the conditions for which temperature aware design is needed.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128775015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 73
Next generation architectures can dramatically reduce the 4G deployment cycle 下一代架构可以大大缩短4G部署周期
Design, Automation and Test in Europe Pub Date : 2006-03-06 DOI: 10.1109/DATE.2006.243992
D. Shaver
{"title":"Next generation architectures can dramatically reduce the 4G deployment cycle","authors":"D. Shaver","doi":"10.1109/DATE.2006.243992","DOIUrl":"https://doi.org/10.1109/DATE.2006.243992","url":null,"abstract":"Summary form only given. We have been \"talking\" about 4G systems emerging in 2010 for many years. However, to deploy these systems in 2010, we should already know with high confidence the 4G signal processing and SoC architectures for 4G handsets. It realistically takes 2 years to develop a power-efficient, cost competitive system-on-a-chip (SoC) for a volume market. There are standards to be completed, field trials, and wide scale acceptance before a system solution becomes viable. The entire cycle is at least 5 years. But, rather than giving up on 2010 as the year for 4G, we need to continue developing the right signal processing, network protocols, and SoC architectures given our knowledge of Moore's Law, emerging tools sets, and advanced receiver technology, which together facilitate rapid time-to-market of energy efficient solutions. The market winners will quickly adapt to the emerging 4G ecosystem and will develop solutions before others. This talk provides some historical perspectives on architectures and systems evolution with the goal of providing an optimistic view that 4G is very near.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131062207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hogthrob: towards a sensor network infrastructure for sow monitoring (wireless sensor network special day) Hogthrob:面向母猪监测的传感器网络基础设施(无线传感器网络特别日)
Design, Automation and Test in Europe Pub Date : 2006-03-06 DOI: 10.1109/DATE.2006.243977
Philippe Bonnet, Martin Leopold, K. Madsen
{"title":"Hogthrob: towards a sensor network infrastructure for sow monitoring (wireless sensor network special day)","authors":"Philippe Bonnet, Martin Leopold, K. Madsen","doi":"10.1109/DATE.2006.243977","DOIUrl":"https://doi.org/10.1109/DATE.2006.243977","url":null,"abstract":"Summary form only given. We aim at developing a next-generation system for sow monitoring. Today, farmers use RFID based solutions with an ear tag on the sows and a reader located inside the feeding station. This does not allow the farmers to locate a sow in a large pen, or to monitor the life cycle of the sow (detect heat period, detect injury...). Our goal is to explore the design of a sensor network that supports such functionalities and meets the constraints of this industry in terms of price, energy consumption and availability.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133960256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization 面向特定领域优化的粗粒度可重构架构中的资源共享和流水线
Design, Automation and Test in Europe Pub Date : 2005-03-07 DOI: 10.1109/DATE.2005.260
Yoonjin Kim, Mary Kiemb, Chul-Hong Park, Jinyong Jung, Kiyoung Choi
{"title":"Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization","authors":"Yoonjin Kim, Mary Kiemb, Chul-Hong Park, Jinyong Jung, Kiyoung Choi","doi":"10.1109/DATE.2005.260","DOIUrl":"https://doi.org/10.1109/DATE.2005.260","url":null,"abstract":"Coarse-grained reconfigurable architectures aim to achieve goals of both high performance and flexibility. However, existing reconfigurable array architectures require many resources without considering the specific application domain. Functional resources that take long latency and/or large area can be pipelined and/or shared among the processing elements. Therefore, the hardware cost and the delay can be effectively reduced without any performance degradation for some application domains. We suggest such a reconfigurable array architecture template and a design space exploration flow for domain-specific optimization. Experimental results show that our approach is much more efficient, in both performance and area, compared to existing reconfigurable architectures.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115439462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 99
RIP: an efficient hybrid repeater insertion scheme for low power RIP:一种高效的低功率混合中继器插入方案
Design, Automation and Test in Europe Pub Date : 2005-03-07 DOI: 10.1109/DATE.2005.262
Xun Liu, Yuantao Peng, M. Papaefthymiou
{"title":"RIP: an efficient hybrid repeater insertion scheme for low power","authors":"Xun Liu, Yuantao Peng, M. Papaefthymiou","doi":"10.1109/DATE.2005.262","DOIUrl":"https://doi.org/10.1109/DATE.2005.262","url":null,"abstract":"The paper presents a novel repeater insertion algorithm for interconnect power minimization. The novelty of our approach is in the judicious integration of an analytical solver and a dynamic programming based method. Specifically, the analytical solver chooses a concise repeater library and a small set of repeater location candidates such that the dynamic programming algorithm can be performed fast with little degradation of the solution quality. In comparison with previously reported repeater insertion schemes, within comparable runtimes, our approach achieves up to 37% higher power savings. Moreover, for the same design quality, our scheme attains a speedup of two orders of magnitude.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114659687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Testing logic cores using a BIST P1500 compliant approach: a case of study 使用符合BIST P1500的方法测试逻辑核:一个研究案例
Design, Automation and Test in Europe Pub Date : 2005-03-07 DOI: 10.1109/DATE.2005.305
P. Bernardi, G. Masera, F. Quaglio, M. Reorda
{"title":"Testing logic cores using a BIST P1500 compliant approach: a case of study","authors":"P. Bernardi, G. Masera, F. Quaglio, M. Reorda","doi":"10.1109/DATE.2005.305","DOIUrl":"https://doi.org/10.1109/DATE.2005.305","url":null,"abstract":"In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in system-on-a-chip (SoC) environments. The approach advantages are the ability to protect the core IP, the simple test interface (thanks also to the adoption of the P1500 standard), the possibility to run the test at-speed, the reduced test time, and the good diagnostic capabilities. The paper reports figures of the achieved fault coverage, the required area overhead, and the performance slowdown, and compares the figures with those for alternative approaches, such as those based on full scan and sequential ATPG.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127108393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
BB-GC: basic-block level garbage collection BB-GC:基本块级垃圾收集
Design, Automation and Test in Europe Pub Date : 2005-03-07 DOI: 10.1109/DATE.2005.80
O. Ozturk, M. Kandemir, M. J. Irwin
{"title":"BB-GC: basic-block level garbage collection","authors":"O. Ozturk, M. Kandemir, M. J. Irwin","doi":"10.1109/DATE.2005.80","DOIUrl":"https://doi.org/10.1109/DATE.2005.80","url":null,"abstract":"Memory space limitation is a serious problem for many embedded systems from diverse application domains. While circuit/packaging techniques are definitely important to squeeze large quantities of data/instruction into small size memories typically employed by embedded systems, software can also play a crucial role in reducing memory space demands of embedded applications. This paper focuses on a software-managed two-level memory hierarchy and instruction accesses. Our goal is to reduce on-chip memory requirements of a given application as much as possible, so that the memory space saved can be used by other simultaneously-executing applications. The proposed approach achieves this by tracking the lifetime of instructions. Specifically, when an instruction is dead (i.e. it could not be visited again in the rest of execution), we deallocate the on-chip memory space allocated to it. Working on the control flow graph representation of an embedded application, our approach performs basic block-level garbage collection for on-chip memories.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127277068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Buffer insertion considering process variation 考虑过程变化的缓冲器插入
Design, Automation and Test in Europe Pub Date : 2005-03-07 DOI: 10.1109/DATE.2005.85
Jinjun Xiong, K. Tam, Lei He
{"title":"Buffer insertion considering process variation","authors":"Jinjun Xiong, K. Tam, Lei He","doi":"10.1109/DATE.2005.85","DOIUrl":"https://doi.org/10.1109/DATE.2005.85","url":null,"abstract":"A comprehensive probabilistic methodology is proposed to solve the buffer insertion problem with the consideration of process variations. In contrast to a recent work, we point out, for the first time, that the correlation between the required arrival time and the downstream loading capacitance must be considered in order to solve the problem \"correctly\". We develop an efficient bottom-up recursive algorithm to calculate the joint probability density function that accurately captures the above correlation, and propose effective pruning rules to exclude probabilistically inferior solutions. We verify our buffer insertion using timing analysis with both device and interconnect variations, and show that compared to the conventional buffer insertion algorithm using nominal device and interconnect parameters, our new buffer insertion methodology can reduce the probability of timing violation by up to 30%.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127367690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Platform based design for automotive sensor conditioning 基于平台的汽车传感器调理设计
Design, Automation and Test in Europe Pub Date : 2005-03-07 DOI: 10.1109/DATE.2005.240
L. Fanucci, A. Giambastiani, F. Iozzi, C. Marino, A. Rocchi
{"title":"Platform based design for automotive sensor conditioning","authors":"L. Fanucci, A. Giambastiani, F. Iozzi, C. Marino, A. Rocchi","doi":"10.1109/DATE.2005.240","DOIUrl":"https://doi.org/10.1109/DATE.2005.240","url":null,"abstract":"A general architecture suitable for interfacing several kinds of sensors for automotive applications is presented. A platform based design approach is pursued to improve system performance while minimizing time-to-market. The platform is composed of an analog front-end and a digital section. The latter is based on a microcontroller core (8051 IP by Oregano) plus a set of hardware dedicated to the complex signal processing required for sensor conditioning. The microcontroller also handles the communication with external devices (such as a PC) for data output and fast prototyping. A case study is presented concerning the conditioning of a gyro yaw rate sensor for automotive applications. Measured performance results outperform current state-of-the-art commercial devices.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126173001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Direct conversion pulsed UWB transceiver architecture 直接转换脉冲超宽带收发器结构
Design, Automation and Test in Europe Pub Date : 2005-03-07 DOI: 10.1109/DATE.2005.122
R. Blázquez, F. S. Lee, D. Wentzloff, B. Ginsburg, J. Powell, A. Chandrakasan
{"title":"Direct conversion pulsed UWB transceiver architecture","authors":"R. Blázquez, F. S. Lee, D. Wentzloff, B. Ginsburg, J. Powell, A. Chandrakasan","doi":"10.1109/DATE.2005.122","DOIUrl":"https://doi.org/10.1109/DATE.2005.122","url":null,"abstract":"Ultra-wideband (UWB) communication is an emerging wireless technology that promises high data rates over short distances and precise locationing. The large available bandwidth and the constraint of a maximum power spectral density drives a unique set of system challenges. This paper addresses these challenges using two UWB transceivers and a discrete prototype platform.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123326830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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