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Design, Automation and Test in Europe最新文献

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A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements 一种新的基于缓存利用率的动态电压频率缩放(DVFS)机制来增强可靠性
Design, Automation and Test in Europe Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0067
Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, A. Wu, TingTing Hwang
{"title":"A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements","authors":"Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, A. Wu, TingTing Hwang","doi":"10.3850/9783981537079_0067","DOIUrl":"https://doi.org/10.3850/9783981537079_0067","url":null,"abstract":"We propose a cache architecture using a 7T/14T SRAM [1] and a control mechanism for reliability enhancements. Our control mechanism differs from the conventional DVFS methods, which considers not only the CPI behaviors but also the cache utilizations. To measure cache utilization, a novel metric is proposed. The experimental results show that our proposed method achieves thousand times less bit-error occurrences compared to the conventional DVFS methods under the ultra-low voltage operation. Moreover, the results show that our proposed method surprisingly not only incurs no performance and energy overheads but also achieves on an average 5.1% performance improvement and 5% energy reduction compared to the conventional DVFS methods.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114317512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel inexact memory aware algorithm co-design for energy efficient computation: algorithmic principles 面向节能计算的新型非精确内存感知算法协同设计:算法原理
Design, Automation and Test in Europe Pub Date : 2015-03-09 DOI: 10.7873/DATE.2015.1114
Guru Prakash Arumugam, Prashanth Srikanthan, John E. Augustine, K. Palem, E. Upfal, Ayush Bhargava, P. ., Sreelatha Yenugula
{"title":"Novel inexact memory aware algorithm co-design for energy efficient computation: algorithmic principles","authors":"Guru Prakash Arumugam, Prashanth Srikanthan, John E. Augustine, K. Palem, E. Upfal, Ayush Bhargava, P. ., Sreelatha Yenugula","doi":"10.7873/DATE.2015.1114","DOIUrl":"https://doi.org/10.7873/DATE.2015.1114","url":null,"abstract":"It is increasingly accepted that energy savings can be achieved by trading the accuracy of a computing system for energy gains---quite often significantly. This approach is referred to as inexact or approximate computing. Given that a significant portion of the energy in a modern general purpose processor is spent on moving data to and from storage, and that increasingly data movement contributes significantly to activity during the execution of applications, it is important to be able to develop techniques and methodologies for inexact computing in this context. To accomplish this to its fullest level, it is important to start with algorithmic specifications and alter their intrinsic design to take advantage of inexactness. This calls for a new approach to inexact memory aware algorithm design (IMAD) or co-design. In this paper, we provide the theoretical foundations which include novel models as well as technical results in the form of upper and lower bounds for IMAD in the context of universally understood and canonical problems: variations of sorting, and string matching. Surprisingly, IMAD allowed us to design entirely error-free algorithms while achieving energy gain factors of 1.5 and 5 in the context of sorting and string matching when compared to their traditional (textbook) algorithms. IMAD is also amenable to theoretical analysis and we present several asymptotic bounds on energy gains.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122138186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Panel: Future SoC verification methodology: UVM evolution or revolution? 专题讨论:未来SoC验证方法:UVM演进还是革命?
Design, Automation and Test in Europe Pub Date : 2014-03-24 DOI: 10.5555/2616606.2617129
R. Drechsler, C. Chevallaz, F. Fummi, A. Hu, Ronny Morad, F. Schirrmeister, A. Goryachev
{"title":"Panel: Future SoC verification methodology: UVM evolution or revolution?","authors":"R. Drechsler, C. Chevallaz, F. Fummi, A. Hu, Ronny Morad, F. Schirrmeister, A. Goryachev","doi":"10.5555/2616606.2617129","DOIUrl":"https://doi.org/10.5555/2616606.2617129","url":null,"abstract":"With increasing design complexity System on Chip (SoC) verification is becoming a more and more important and challenging aspect of the overall development process. The Universal Verification Methodology (UVM) is thereby a common solution to this problem; although it still keeps some problems unsolved. In this panel leading experts from industry (both users and vendors) and academy will discuss the future of SoC verification methodology.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"111 3S 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123129359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Panel: Emerging vs. established technologies, a two sphinxes' riddle at the crossroads? 专题讨论:新兴技术与成熟技术，十字路口的两个狮身人面像之谜?
Design, Automation and Test in Europe Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.016
M. Casale-Rossi, G. Micheli, R. Aitken, A. Domic, M. Horstmann, R. Hum, P. Magarshack
{"title":"Panel: Emerging vs. established technologies, a two sphinxes' riddle at the crossroads?","authors":"M. Casale-Rossi, G. Micheli, R. Aitken, A. Domic, M. Horstmann, R. Hum, P. Magarshack","doi":"10.7873/DATE.2014.016","DOIUrl":"https://doi.org/10.7873/DATE.2014.016","url":null,"abstract":"Crossroads have always been challenging: they require a decision; in Egyptian and Greek mythology they were often guarded by two sphinxes trying to cheat the traveler with their riddles. The two sphinxes, the knight and the knave, the lady and the tiger, are just few instances of difficult puzzles that have kept logicians and mathematicians busy for the last 5,000 years. Today, you are walking down Moore's Law road when you come to a crossroads: one road brings you into the land of emerging technologies: 14, 10 and 7 nanometer, FDSOI, FinFET, 3D-IC,... beyond and below; the other road holds you into the land of established technologies: 28, 40, 65, and 90 nanometers, possibly even above, AM unlike the sphinxes, they will strive to provide you with honest advice about the “road conditions”, and you are allowed to ask multiple questions to them to figure out which road is the best for you.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122314865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Dynamic construction of circuits for reactive traffic in homogeneous CMPs 均匀cmp中无功流量电路的动态构造
Design, Automation and Test in Europe Pub Date : 2014-03-24 DOI: 10.7873/DATE2014.254
Marta Ortin, Dario Suarez, Maria Villarroya, C. Izu, V. Viñals
{"title":"Dynamic construction of circuits for reactive traffic in homogeneous CMPs","authors":"Marta Ortin, Dario Suarez, Maria Villarroya, C. Izu, V. Viñals","doi":"10.7873/DATE2014.254","DOIUrl":"https://doi.org/10.7873/DATE2014.254","url":null,"abstract":"Networks on Chip (NoCs) have a large impact on system performance, area and energy. Considering the characteristics of the memory subsystem while designing the NoC helps identify improvement opportunities and build more efficient designs. Leveraging the frequent request-reply pattern, our proposal dynamically builds the reply path in advance, is able to share circuits between messages, and even removes some implicit replies, significantly reducing NoC latency. A careful implementation of this circuit reservation mechanism achieves an average 17% reduction in router energy consumption, 8% smaller router area and a 2% system performance increase, compared with its baseline counterpart.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126196298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Panel: The world is going... analog & mixed-signal! What about EDA? 小组:世界正在走向……模拟和混合信号!EDA呢?
Design, Automation and Test in Europe Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.050
M. Casale-Rossi, Pietro Palella, Mario Anton, O. Galzur, R. Hum, R. Kress, P. Lo
{"title":"Panel: The world is going... analog & mixed-signal! What about EDA?","authors":"M. Casale-Rossi, Pietro Palella, Mario Anton, O. Galzur, R. Hum, R. Kress, P. Lo","doi":"10.7873/DATE.2014.050","DOIUrl":"https://doi.org/10.7873/DATE.2014.050","url":null,"abstract":"Contrarily to a common belief, the world is not going digital! Analog and mixed-signal electronics is more and more important and yet pervasive. This is due both to the increasing systems integration, by nature leading to heterogeneity, and to the complex, digital computing functions being complemented by scores of on-chip analog functions, interfacing/interacting with people, environment, and other systems. Specialty silicon foundries are now stable members of top ten revenue rankings. This technology trend demands for more design automation in both implementation and verification domains. Lossless interfaces between digital and analog design environments, multi-technology support, mixed-signal simulation engines - but also debugging aids - are no longer a nice to have. According to IBS [1], the cost of implementing and verifying the mixed-signal functions is generally over 50% of the design costs even though the mixed-signal transistors can be as low as 3% of the total! What are the critical requirement, moving forward, and what is EDA industry doing to serve the needs of this increasingly important semiconductor industry segment?","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127442951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Exploring the limits of phase change memories 探索相变记忆的极限
Design, Automation and Test in Europe Pub Date : 2014-03-24 DOI: 10.7873/DATE2014.280
M. Wuttig
{"title":"Exploring the limits of phase change memories","authors":"M. Wuttig","doi":"10.7873/DATE2014.280","DOIUrl":"https://doi.org/10.7873/DATE2014.280","url":null,"abstract":"Phase change materials are among the most promising compounds in information technology. They can be very rapidly switched between the amorphous and the crystalline state, indicative for peculiar crystallization behaviour. Phase change materials are already employed in rewriteable optical data storage, where the pronounced difference of optical properties between the amorphous and crystalline state is used. This unconventional class of materials is also the basis of a storage concept to replace flash memory. This talk will discuss the unique material properties which characterize phase change materials. In particular, it will be shown that the crystalline state of phase change materials is characterized by the occurrence of resonant bonding, a particular flavour of covalent bonding. This insight is employed to predict systematic property trends and to develop non-volatile memories with DRAM-like switching speeds potentially paving the road towards a universal memory. Phase change materials do not only provide exciting opportunities for applications including ‘greener’ storage devices, but also form a unique quantum state of matter as will be demonstrated by transport measurements. In this talk, potential limits of phase change memories in terms of switching speed, scalability and power consumption will be discussed.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122222772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The connected car and its implication to the automotive chip roadmap 互联汽车及其对汽车芯片路线图的意义
Design, Automation and Test in Europe Pub Date : 2014-03-24 DOI: 10.7873/DATE2014.179
M. Bolle
{"title":"The connected car and its implication to the automotive chip roadmap","authors":"M. Bolle","doi":"10.7873/DATE2014.179","DOIUrl":"https://doi.org/10.7873/DATE2014.179","url":null,"abstract":"The automotive industry is in a radical change process driven by technology. On the one hand side the proliferation of communication technologies into the car leads to internet connected vehicles. The vehicle will become an integral part of the internet — opening new processing paradigms for the car itself. On the other hand the vehicle itself significantly expands its sensor and processing capabilities by the use of radar, video, ultrasound sensors and usage of state of the art CPU and GPU processor architectures. In our talk we will address both developments and outline foreseen future applications as future driving assistant and infotainment systems as well as highly automated driving. We will discuss major requirements for the future electrical architectures and implications for future automotive chips.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125964728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thinfilm printed ferro-electric memories and integrated products 薄膜印刷铁电存储器及集成产品
Design, Automation and Test in Europe Pub Date : 2014-03-24 DOI: 10.7873/DATE2014.283
C. Karlsson, Peter Fischer
{"title":"Thinfilm printed ferro-electric memories and integrated products","authors":"C. Karlsson, Peter Fischer","doi":"10.7873/DATE2014.283","DOIUrl":"https://doi.org/10.7873/DATE2014.283","url":null,"abstract":"Printed electronics has recently moved from a focus on the production of individual components towards the design and initial commercialization of integrated systems. This paper describes the current status and further trends of ferroelectric nonvolatile memories as developed and produced by Thin Film Electronics.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"30 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123158754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Memcomputing: The cape of good hope: [Extended special session description] Memcomputing:美好的希望之角:[扩展特别会议描述]
Design, Automation and Test in Europe Pub Date : 2014-03-24 DOI: 10.7873/DATE.2014.277
Yiyu Shi, Hung-Ming Chen
{"title":"Memcomputing: The cape of good hope: [Extended special session description]","authors":"Yiyu Shi, Hung-Ming Chen","doi":"10.7873/DATE.2014.277","DOIUrl":"https://doi.org/10.7873/DATE.2014.277","url":null,"abstract":"Energy efficiency has emerged as a major barrier to performance scalability for modern processors. On the other hand, significant breakthroughs have been achieved in memory technologies recently [1-4, 6]. As such, the fascinating idea of memcomputing (i.e., use memory for computation purposes) has drawn wide attention from both academia and industry as an effective remedy. Compared with conventional logic computing, memory array provides large set of parallel resources with high bandwidth, which can be configured to perform in-situ computing and information processing, leading to drastic reduction in processor-memory traffic. It will not only make computations more power-and speed-efficient, but also smarter. In addition, it exploits the advances in memory technologies (e.g., [8, 9]) and integration approaches (e.g. 3D integration [11-17]) to achieve better technology scalability. This special session includes three presentations that offer a broad-spectrum retreat on this hot topic.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121885840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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