Panel: Future SoC verification methodology: UVM evolution or revolution?

R. Drechsler, C. Chevallaz, F. Fummi, A. Hu, Ronny Morad, F. Schirrmeister, A. Goryachev
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引用次数: 12

Abstract

With increasing design complexity System on Chip (SoC) verification is becoming a more and more important and challenging aspect of the overall development process. The Universal Verification Methodology (UVM) is thereby a common solution to this problem; although it still keeps some problems unsolved. In this panel leading experts from industry (both users and vendors) and academy will discuss the future of SoC verification methodology.
专题讨论:未来SoC验证方法:UVM演进还是革命?
随着设计复杂性的增加,片上系统(SoC)验证在整个开发过程中变得越来越重要和具有挑战性。因此,通用验证方法(UVM)是这个问题的通用解决方案;尽管它仍然有一些问题没有解决。在这个小组中,来自业界(用户和供应商)和学术界的领先专家将讨论SoC验证方法的未来。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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