R. Drechsler, C. Chevallaz, F. Fummi, A. Hu, Ronny Morad, F. Schirrmeister, A. Goryachev
{"title":"专题讨论:未来SoC验证方法:UVM演进还是革命?","authors":"R. Drechsler, C. Chevallaz, F. Fummi, A. Hu, Ronny Morad, F. Schirrmeister, A. Goryachev","doi":"10.5555/2616606.2617129","DOIUrl":null,"url":null,"abstract":"With increasing design complexity System on Chip (SoC) verification is becoming a more and more important and challenging aspect of the overall development process. The Universal Verification Methodology (UVM) is thereby a common solution to this problem; although it still keeps some problems unsolved. In this panel leading experts from industry (both users and vendors) and academy will discuss the future of SoC verification methodology.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"111 3S 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"Panel: Future SoC verification methodology: UVM evolution or revolution?\",\"authors\":\"R. Drechsler, C. Chevallaz, F. Fummi, A. Hu, Ronny Morad, F. Schirrmeister, A. Goryachev\",\"doi\":\"10.5555/2616606.2617129\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With increasing design complexity System on Chip (SoC) verification is becoming a more and more important and challenging aspect of the overall development process. The Universal Verification Methodology (UVM) is thereby a common solution to this problem; although it still keeps some problems unsolved. In this panel leading experts from industry (both users and vendors) and academy will discuss the future of SoC verification methodology.\",\"PeriodicalId\":205976,\"journal\":{\"name\":\"Design, Automation and Test in Europe\",\"volume\":\"111 3S 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-03-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Design, Automation and Test in Europe\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.5555/2616606.2617129\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Design, Automation and Test in Europe","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.5555/2616606.2617129","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Panel: Future SoC verification methodology: UVM evolution or revolution?
With increasing design complexity System on Chip (SoC) verification is becoming a more and more important and challenging aspect of the overall development process. The Universal Verification Methodology (UVM) is thereby a common solution to this problem; although it still keeps some problems unsolved. In this panel leading experts from industry (both users and vendors) and academy will discuss the future of SoC verification methodology.
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