交互式演示:聚类VLIW-ASP的DSE的时间约束聚类

Mario Schölzel
{"title":"交互式演示:聚类VLIW-ASP的DSE的时间约束聚类","authors":"Mario Schölzel","doi":"10.1145/1266366.1266465","DOIUrl":null,"url":null,"abstract":"In this paper we describe a new time-constrained clustering algorithm. It is coupled with a time-constrained scheduling algorithm and used for Design-Space-Exploration (DSE) of clustered VLIW processors with heterogeneous clusters and heterogeneous functional units. The algorithm enables us to reduce the complexity of the DSE, because the parameters of the VLIW are derived from the clustered schedule of the considered application which is produced during a single compilation step. Several compilations of the same application with different VLIW-parameter settings are not necessary. Our proposed algorithm is integrated into a DSE-Tool in order to explore the best parameters of a clustered VLIW processor for several basic blocks of signal processing applications. The obtained results are compared to the results of Lapinskii's work and show, that, for most benchmarks, we are able to save ports in the register file of each cluster.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Interactive presentation: Time-constrained clustering for DSE of clustered VLIW-ASP\",\"authors\":\"Mario Schölzel\",\"doi\":\"10.1145/1266366.1266465\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we describe a new time-constrained clustering algorithm. It is coupled with a time-constrained scheduling algorithm and used for Design-Space-Exploration (DSE) of clustered VLIW processors with heterogeneous clusters and heterogeneous functional units. The algorithm enables us to reduce the complexity of the DSE, because the parameters of the VLIW are derived from the clustered schedule of the considered application which is produced during a single compilation step. Several compilations of the same application with different VLIW-parameter settings are not necessary. Our proposed algorithm is integrated into a DSE-Tool in order to explore the best parameters of a clustered VLIW processor for several basic blocks of signal processing applications. The obtained results are compared to the results of Lapinskii's work and show, that, for most benchmarks, we are able to save ports in the register file of each cluster.\",\"PeriodicalId\":205976,\"journal\":{\"name\":\"Design, Automation and Test in Europe\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-04-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Design, Automation and Test in Europe\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1266366.1266465\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Design, Automation and Test in Europe","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1266366.1266465","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

本文描述了一种新的时间约束聚类算法。该算法与时间约束调度算法相结合,用于具有异构集群和异构功能单元的集群VLIW处理器的设计-空间探索(DSE)。该算法使我们能够降低DSE的复杂性,因为VLIW的参数是从在单个编译步骤中生成的所考虑的应用程序的集群调度中派生出来的。没有必要使用不同的vliw参数设置对同一个应用程序进行多次编译。我们提出的算法集成到一个DSE-Tool中,以探索集群VLIW处理器的几个基本信号处理应用的最佳参数。将获得的结果与Lapinskii的工作结果进行比较,并表明,对于大多数基准测试,我们能够在每个集群的寄存器文件中保存端口。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Interactive presentation: Time-constrained clustering for DSE of clustered VLIW-ASP
In this paper we describe a new time-constrained clustering algorithm. It is coupled with a time-constrained scheduling algorithm and used for Design-Space-Exploration (DSE) of clustered VLIW processors with heterogeneous clusters and heterogeneous functional units. The algorithm enables us to reduce the complexity of the DSE, because the parameters of the VLIW are derived from the clustered schedule of the considered application which is produced during a single compilation step. Several compilations of the same application with different VLIW-parameter settings are not necessary. Our proposed algorithm is integrated into a DSE-Tool in order to explore the best parameters of a clustered VLIW processor for several basic blocks of signal processing applications. The obtained results are compared to the results of Lapinskii's work and show, that, for most benchmarks, we are able to save ports in the register file of each cluster.
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