M. Casale-Rossi, P. Leduc, G. Micheli, P. Blouet, B. Farley, A. Fontanelli, D. Milojevic, Steve Smith
{"title":"Panel: \"will 3D-IC remain a technology of the future... even in the future?\"","authors":"M. Casale-Rossi, P. Leduc, G. Micheli, P. Blouet, B. Farley, A. Fontanelli, D. Milojevic, Steve Smith","doi":"10.7873/DATE.2013.310","DOIUrl":"https://doi.org/10.7873/DATE.2013.310","url":null,"abstract":"If asked \"who needs faster planes?\" the vast majority of the 2.75 billion airline passengers (source: IATA 2011) would say that they do need faster planes, and that they need them right now. Still, the commercial aircrafts cruising speed has remained the same -- 800 km/hour -- over the last 50+ years, and after the sad end of the Concorde project, neither Airbus nor Boeing are seriously working on the topic. Along the same lines, when asked \"who needs 3D-IC?\", most IC designers say that they desperately need 3D-IC to keep advancing electronic products performance, whilst addressing the needs of higher bandwidth, lower cost, heterogeneous integration, and power constraints. Still, 3D-IC continues to be the technology of the future. What are the road blocks towards 3D-IC adoption? Is it process technology, foundry or OSAT commercial offering, or EDA, or the business economics that is holding 3D-IC on the ground? In the introductory presentation of this panel session, LETI Patrick Leduc will illustrate the state-of-the-art of commercial, mainstream 3D-IC. EPFL Professor Giovanni de Micheli will then moderate an industry and research panel, to understand what are the key factors preventing 3D-IC from becoming the technology of today.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"153 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131285443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The mobile society: chances and challenges for micro- and power electronics","authors":"K. Meder","doi":"10.1109/DATE.2012.6176421","DOIUrl":"https://doi.org/10.1109/DATE.2012.6176421","url":null,"abstract":"Klaus Meder will demonstrate how the increasing society's request for a widespread mobility together with the need to save energy resources generates opportunities for a broad spectrum of new electronic systems - as well as some challenges for the KETs Design, semiconductor technologies and assembly. Bosch is the leading automotive supplier worldwide with more than 280 manufacturing sites including a semiconductor fab in Reutlingen, Germany.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114879216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"New foundry models - accelerations in transformations of the semiconductor industry","authors":"M. Chian","doi":"10.1109/DATE.2012.6176422","DOIUrl":"https://doi.org/10.1109/DATE.2012.6176422","url":null,"abstract":"Mojy Chian will give an outlook on the future development and role of foundries, focusing on the new collaborative approach in technology development and high-end manufacturing. GLOBAL FOUNDRIES is the first foundry with global footprint and leading edge manufacturing sites in Dresden, Germany, Singapore and the US.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116260563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Accelerators and emulators: can they become the platform of choice for hardware verification?","authors":"B. Al-Hashimi, Ronny Morad","doi":"10.5555/2492708.2492817","DOIUrl":"https://doi.org/10.5555/2492708.2492817","url":null,"abstract":"The verification of modern hardware designs requires an enormous amount of simulation resources. A growing trend in the industry is the use of accelerators and emulators to support this effort.\u0000 Because they are very fast compared to software simulators, accelerators and emulators provide the opportunity to significantly shorten the verification cycle. However, for this to happen challenges in all main aspects of the verification process (test-generation, checking, coverage and debugging) will first need to be solved.\u0000 In this panel session, experts from both academia and industry (EDA vendors and users) will come together to present their ideas and experiences on how to best utilize accelerators and emulators to enhance the verification process.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129086176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Embedded tutorial: Addressing critical power management verification issues in low power designs","authors":"B. Kapoor, K. M. Just","doi":"10.1109/DATE.2011.5763029","DOIUrl":"https://doi.org/10.1109/DATE.2011.5763029","url":null,"abstract":"Summary form only given. Power management techniques that leverage voltage as a handle are being extensively used in power sensitive designs. These techniques include power gating, power gating with retention, multiple supply voltages, dynamic voltage scaling, adaptive voltage scaling, multi-threshold CMOS, and active body bias. The use of the power management techniques also imply new challenges in validation and testing of designs as new power states are created. We look into verification issues along with the solutions to these issues using a verification strategy that involves power-aware simulation, rule-based structural checking, formal tools, and methodology recommendations. We detail our varied experiences with various design teams in addressing these low power verification issues for applications such as the wireless handset, low power microprocessors, and GPS.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122166171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Logic synthesis and physical design: Quo vadis?","authors":"G. Micheli","doi":"10.1109/DATE.2011.5763015","DOIUrl":"https://doi.org/10.1109/DATE.2011.5763015","url":null,"abstract":"Virtually all current integrated circuits and systems would not exist without the use of logic synthesis and physical design tools. These design technologies were developed in the last fifty years and it is hard to say if they have come to full maturity. Physical design evolved from methods used for printed-circuit boards, where the classic problems of placement and routing surfaced for the first time [1]. Logic synthesis evolved in a different trajectory, starting from the classic works on switching theory [2], but took a sharp turn in the eighties when multi-level logic synthesis, coupled to semicustom technologies, provided designers with a means to map models in hardware description languages into netlists ready for physical design [3],[4]. The clear separation between logic and physical design tasks enabled the development of effective design tool flows, where signoff could be done at the netlist level. Nevertheless, the relentless downscaling of semiconductor technologies forced this separation to disappear, once circuit delays became interconnect-dominated. Since the nineties, design flows combined logic and physical design tools to address the so-called timing closure problem, i.e., to reduce the designer effort to synthesize a design that satisfies all timing constraints. Despite many efforts in various directions, most notably with the use of the fixed timing methodology, this problem is not completely solved yet. The complexity of integrated logic and physical tool flows, as well as the decrease in design starts of large ASICs, limits the development of these flows to a few EDA companies.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124986445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An electrical test method for MEMS convective accelerometers: Development and evaluation","authors":"A. Rekik, F. Azaïs, N. Dumas, F. Mailly, P. Nouet","doi":"10.1109/DATE.2011.5763137","DOIUrl":"https://doi.org/10.1109/DATE.2011.5763137","url":null,"abstract":"In this paper, an alternative test method for MEMS convective accelerometers is presented. It is first demonstrated that device sensitivity can be determined without the use of physical test stimuli by simple electrical measurements. Using a previously developed behavioral model that allows efficient Monte-Carlo simulations, we have established a good correlation between electrical test parameters and device sensitivity. Proposed test method is finally evaluated for different strategies that privilege yield, fault coverage or test efficiency.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115861193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Panel: What does the power industry need from the EDA industry and what is the EDA industry doing about it?","authors":"P. Wright","doi":"10.1109/DATE.2011.5763243","DOIUrl":"https://doi.org/10.1109/DATE.2011.5763243","url":null,"abstract":"Until recently the electrical power industry has relied solely on traditional technologies — copper and iron as cables, transformers and machines as the mainstream solution for the generation, transmission and distribution of power. Whilst use of these materials and technologies is here to stay, improvements in power semiconductor technology mean that the industry is moving into a position where more and faster control of power systems can be achieved. This high level control requires a sensing and communication infrastructure to be put in place across the network. At the same time, the use of electricity in the home, through the potential of real time consumer pricing requires new technologies. This panel session aims to pull together heavy current electrical power engineers and light current electronic engineers to form a discussion and debate about the future role of EDA in applications which are being brought about by changes in the functioning of the power industry. Power engineers from both industry and academia will stimulate the discussion with requirements both from a system perspective and consumer perspective. The representatives from the EDA side will respond with what contributions they believe EDA can make, what already exists or is a simple development problem and what research issues remain in achieving these goals. In summary, this panel aims to provide motivation for the EDA industry to work on useful technology that can be applied to heavy power systems with a view to improving global energy efficiency.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128571254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Crone, O. Bringmann, C. Chevallaz, B. Dickman, Volkan Esen, M. Rohleder
{"title":"State of the art verification methodologies in 2015","authors":"A. Crone, O. Bringmann, C. Chevallaz, B. Dickman, Volkan Esen, M. Rohleder","doi":"10.1109/DATE.2011.5763215","DOIUrl":"https://doi.org/10.1109/DATE.2011.5763215","url":null,"abstract":"In the last few years, the industry has seen acceleration in the evolution of verification methodologies. While the industry focus has been on enabling a standard based approach to help today's challenges, one can wonder what is needed to prepare us self for the further verification challenges. The expert panelist will discuss the many aspects of verification methodologies, the requirements and predictions for verification methodologies needed 4–5 years from now on.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121646566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Embedded software debug and test: Needs and requirements for innovations in debugging","authors":"M. Winterholer","doi":"10.1109/DATE.2011.5763122","DOIUrl":"https://doi.org/10.1109/DATE.2011.5763122","url":null,"abstract":"Today's complexity of embedded software is steadily increasing. The growing number of processors in a system and the increased communication and synchronization of all components requires scalable debug and test methods for each component as well as the system as a whole. Considering today's cost and time to market sensitivity it is important to find and debug errors as early as possible and to increase the degree of test and debug automation to avoid the loss of quality, cost and time. These challenges are not only requiring new tools and methodologies but also organizational changes since hardware and software developer have to work together to achieve the necessary productivity and quality gain. This panel brings together users and solution provider experienced in debugging embedded systems to discuss requirements for robust systems that are easy to debug.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116744996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}