{"title":"Near-threshold voltage design in nanoscale CMOS","authors":"V. De","doi":"10.7873/DATE.2013.134","DOIUrl":"https://doi.org/10.7873/DATE.2013.134","url":null,"abstract":"Near-Threshold Voltage (NTV) operation of a CMOS design is defined as the voltage-frequency operating point where the energy consumed per compute operation (pJ/op) reaches a minimum, or the energy efficiency (Mops/Watt) peaks. Typically, this operating voltage is above the nominal threshold voltage of the transistor. The peak efficiency is achieved by a balance of switching energy and idle or leakage energy.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128185752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Alternative power supply concepts for self-sufficient wireless sensor nodes by energy harvesting","authors":"R. Kappel, G. Hofer, G. Holweg, T. Herndl","doi":"10.7873/DATE.2013.107","DOIUrl":"https://doi.org/10.7873/DATE.2013.107","url":null,"abstract":"Replacing batteries in wireless sensor nodes by energy harvesting enables a maintenance-free operation and an increasing degree of miniaturization at the cost of higher power management efforts. The limited power capability of environmental sources requires a careful investigation of the different harvesting opportunities to find the optimal source in a specific application scenario. Promising resources in the automotive area are kinetic and thermoelectric based harvesters. In this talk physical properties of energy converters are analyzed to show their restrictions and allow power estimation. In addition examples of already established self-sufficient sensors are presented.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123976533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Adaptable, high performance energy harvesters: can energy harvesting deliver enough power for automotive electronics?","authors":"P. Mitcheson","doi":"10.5555/2485288.2485406","DOIUrl":"https://doi.org/10.5555/2485288.2485406","url":null,"abstract":"Energy harvesting has become a very popular research topic over the last 12 years, but has only made an industrial impact in a few areas, noticeably in process plant monitoring, including the water and petrochemical processing industries. Like most technologies, greater adoption needs to be realized if performance is to increase and cost to decrease. Batteries cost only tens of pence per Wh, and whilst harvesters can in theory generate very large amount of energy over a long enough period of operation, a typical harvester can require a capital expenditure of tens to hundreds of pounds, making them unattractive in many applications. The automotive sector is a potential area in which harvesters could provide useful functionality and gain from economies of scale, if they can be made reliable enough with a high enough power density and work well in a wide enough variety of scenarios. Recent work on increasing the power density of energy harvesters has focused on improving the power electronic interface, tuning the resonant frequency of motion-driven harvesters and reducing the power consumption of the load electronics.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115164582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Creating a sustainable information and communication infrastructure","authors":"Massoud Pedram","doi":"10.7873/DATE.2013.015","DOIUrl":"https://doi.org/10.7873/DATE.2013.015","url":null,"abstract":"Modern society's dependence on information and communication infrastructure (ICI) is so deeply entrenched that it should be treated on par with other critical lifelines of our existence, such as water and electricity. As is the case with any true lifeline, ICI must be reliable, affordable, and sustainable. Meeting these requirements (especially sustainability) is a continued critical challenge, which will be the focus of my talk. More precisely, I will provide an overview of information and communication technology trends in light of various societal and environmental mandates followed by a review of technologies, systems, and hardware/software solutions required to create a sustainable ICI.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134235310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Casale-Rossi, A. Sangiovanni-Vincentelli, L. Carloni, B. Courtois, H. Man, A. Domic, J. Rabaey
{"title":"Panel: the heritage of Mead & Conway: what has remained the same, what was missed, what has changed, what lies ahead","authors":"M. Casale-Rossi, A. Sangiovanni-Vincentelli, L. Carloni, B. Courtois, H. Man, A. Domic, J. Rabaey","doi":"10.7873/DATE.2013.049","DOIUrl":"https://doi.org/10.7873/DATE.2013.049","url":null,"abstract":"Thirty-two years ago, Electronics Magazine honored Carver Mead and Lynn Conway with its Achievement Award for their contributions to VLSI chip design. The 'Mead & Conway methods' were being taught at 100+ universities all over the world, and \"not only have helped spawn a common design culture so necessary in the VLSI era, but have greatly increased interaction between university and industry so as to stimulate research by both.\" Concepts such as simplified design methods, new, electronic representations of digital design data, scalable design rules, 'clean' formalized digital interfaces between design and manufacturing, and widely accessible silicon foundries suddenly enabled many thousands of chip designers to create many tens of thousands of chip designs. Today, as Moore's Law -- a term coined by Carver Mead -- has brought as from 10 microns to 10 nanometers, what is the heritage of Mead & Conway?\u0000 UCB Professor Alberto Sangiovanni-Vincentelli will moderate an industry and research panel, to discuss what has remained the same, what was missed, what has changed, and what lies ahead.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126416233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"What designs for coming supercomputers?","authors":"X. Vigouroux","doi":"10.7873/DATE.2013.104","DOIUrl":"https://doi.org/10.7873/DATE.2013.104","url":null,"abstract":"The next grail sought by HPC community is the exascale, 100 times the current scale. This target will not be reached easily as many challenges are uprising. The first challenge, the Energy consumption, has become a strict constraint now with a limit set to 20MW (twice as the current top supercomputers). Multiplying the computing elements will imply to drastically reduce the power consumption of each of them. The second challenge will be to keep it cool as: first the overall power envelope, 20MW, include the energy for cooling and second, because 20MW will be turned into heat by joule effect. And the operating temperature of electronic must be bounded otherwise, the leakage (and thus the power consumption) increases and the reliability decreases. This brings us to a third challenge regarding the reliability of the machine, the number of components will be tremendous, thus, the probability of having failing ones will increase. It has to be managed in such a way that applications will not be impacted by the failures. Finally, The last challenge is related to the software stack of these supercomputers, how will we manage billions of threads, how will we debug it,... New paradigms are currently being studied, for instance Bag of tasks, that try to tackle these aspects. These are the challenges we have to solve!! In this presentation, brightened up with insight into Bull roadmap, we present a possible future.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114829493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chandra K. H. Suresh, E. Yilmaz, S. Ozev, O. Sinanoglu
{"title":"Adaptive reduction of the frequency search space for multi-vdd digital circuits","authors":"Chandra K. H. Suresh, E. Yilmaz, S. Ozev, O. Sinanoglu","doi":"10.7873/DATE.2013.072","DOIUrl":"https://doi.org/10.7873/DATE.2013.072","url":null,"abstract":"Increasing process variations, coupled with the need for highly adaptable circuits, bring about tough new challenges in terms of circuit testing. Circuit adaptation for process and workload variability require costly characterization/test cycles for each chip, in order to extract particular V dd /f max behavior of the die under test. This paper aims at adaptively reducing the search space for f max at multiple levels by reusing the information previously obtained from the DUT during test-time. The proposed adaptive solution reduces the test/characterization time and costs at no area or test overhead.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132210698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Ultra-low power: an EDA challenge","authors":"C. Grimm, Javier Moreno, Xiao Pan","doi":"10.7873/DATE.2013.109","DOIUrl":"https://doi.org/10.7873/DATE.2013.109","url":null,"abstract":"Visions such as the internet of things require vast amount of sensors distributed in our environment that strongly rely on circuits that are energy autonomous. However, design of such circuits is a challenge that is currently done by experts only. The challenge is to cope with circuit level design and even technology while designing an application. Unfortunately, tools and methods that support cross-layer and cross-domain optimizations are missing.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115973577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Kazmierski, Leran Wang, B. Al-Hashimi, G. Merrett
{"title":"DoE-based performance optimization of energy management in sensor nodes powered by tunable energy-harvesters","authors":"T. Kazmierski, Leran Wang, B. Al-Hashimi, G. Merrett","doi":"10.7873/DATE.2013.110","DOIUrl":"https://doi.org/10.7873/DATE.2013.110","url":null,"abstract":"An energy-harvester-powered wireless sensor node is a complicated system with many design parameters. To investigate the various trade-offs among these parameters, it is desirable to explore the multi-dimensional design space quickly. However, due to the large number of parameters and costly simulation CPU times, it is often difficult or even impossible to explore the design space via simulation. A design of experiment (DoE) approach using the response surface model (RSM) technique can enable fast design space exploration of a complete wireless sensor node powered by a tunable energy harvester. As a proof of concept, a software toolkit has been developed which implements the DoE-based design flow and incorporates the energy harvester, tuning controller and wireless sensor node. Several test scenarios are considered, which illustrate how the proposed approach permits the designer to adjust a wide range of system parameters and evaluate the effect almost instantly but still with high accuracy..","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116666386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Configurable I/O integration to reduce system-on-chip time to market: DDR, PCIe examples","authors":"F. Martin, P. Bennett","doi":"10.7873/DATE.2013.047","DOIUrl":"https://doi.org/10.7873/DATE.2013.047","url":null,"abstract":"The availability of protocol features with iterative configurability is central to the successful adoption of reusable IP in SoC development. However, the promise of ultimately shrinking the SoC development TTM whilst also allowing greater resourcing efficiency can only be realized with a comprehensive approach to delivering the software, digital and analog components of the protocol to the SoC top level integration as IP subsystems with the correct integration views. This talk will discuss quantitatively how the combination of configurability, quality and integration at the IO protocol can systematically reduce the SoC development and resource plan. It will be demonstrated with examples for DDR and PCIe IO protocols as well as examples from application specific SoC's.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128883655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}