Logic synthesis and physical design: Quo vadis?

Abstract

Virtually all current integrated circuits and systems would not exist without the use of logic synthesis and physical design tools. These design technologies were developed in the last fifty years and it is hard to say if they have come to full maturity. Physical design evolved from methods used for printed-circuit boards, where the classic problems of placement and routing surfaced for the first time [1]. Logic synthesis evolved in a different trajectory, starting from the classic works on switching theory [2], but took a sharp turn in the eighties when multi-level logic synthesis, coupled to semicustom technologies, provided designers with a means to map models in hardware description languages into netlists ready for physical design [3],[4]. The clear separation between logic and physical design tasks enabled the development of effective design tool flows, where signoff could be done at the netlist level. Nevertheless, the relentless downscaling of semiconductor technologies forced this separation to disappear, once circuit delays became interconnect-dominated. Since the nineties, design flows combined logic and physical design tools to address the so-called timing closure problem, i.e., to reduce the designer effort to synthesize a design that satisfies all timing constraints. Despite many efforts in various directions, most notably with the use of the fixed timing methodology, this problem is not completely solved yet. The complexity of integrated logic and physical tool flows, as well as the decrease in design starts of large ASICs, limits the development of these flows to a few EDA companies.