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2013 23rd International Conference on Field programmable Logic and Applications最新文献

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Hardware-efficient implementation of a Femtocell/Macrocell interference-mitigation technique for high-performance LTE-based systems 基于高性能lte系统的Femtocell/Macrocell干扰缓解技术的硬件高效实现
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645585
Oriol Font-Bach, N. Bartzoudis, M. Payaró, A. Pascual-Iserte
{"title":"Hardware-efficient implementation of a Femtocell/Macrocell interference-mitigation technique for high-performance LTE-based systems","authors":"Oriol Font-Bach, N. Bartzoudis, M. Payaró, A. Pascual-Iserte","doi":"10.1109/FPL.2013.6645585","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645585","url":null,"abstract":"This paper presents the FPGA design of an interference-aware digital front end tailored for heterogeneous multi-cell LTE-based systems. A resource-optimized RTL architecture has been implemented and validated under realistic operating conditions using the GEDOMIS® testbed. The parallelization and concurrent resource utilization of the joint synchronization and interference detection processing blocks is covered with low-level details.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124471951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A high-performance IPV6 lookup engine on FPGA 基于FPGA的高性能IPV6查找引擎
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645558
Thilan Ganegedara, V. Prasanna
{"title":"A high-performance IPV6 lookup engine on FPGA","authors":"Thilan Ganegedara, V. Prasanna","doi":"10.1109/FPL.2013.6645558","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645558","url":null,"abstract":"We present a routing table partitioning based solution for a high-performance IPv6 packet lookup engine on Field Programmable Gate Arrays (FPGAs). Based on the statistics collected from real-life backbone IPv6 routing tables, we propose a partitioning algorithm that creates both disjoint and balanced prefix groups. For each partition a range tree is built to perform IPv6 lookup. These range trees are mapped onto independent pipelines on FPGA such that for a single IPv6 lookup, only one partition is active. This yields high dynamic power efficiency via selective stage memory enabling. The balanced partitioning enables us to exploit the memory layout of the FPGA to align the pipeline with the on-chip memory blocks for enhanced performance and resource usage. Post place-and-route results on a state-of-the-art FPGA platform shows that a throughput of 200+ Gbps can be achieved for a 1 million entry IPv6 routing table.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"4 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113961671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A FPGA design for high speed feature extraction from a compressed measurement stream 一种用于从压缩测量流中高速提取特征的FPGA设计
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645527
D. Richmond, R. Kastner, A. Irturk, John McGarry
{"title":"A FPGA design for high speed feature extraction from a compressed measurement stream","authors":"D. Richmond, R. Kastner, A. Irturk, John McGarry","doi":"10.1109/FPL.2013.6645527","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645527","url":null,"abstract":"A common type of triangulation-based active 3D scanner outputs sets of surface coordinates, called profiles, by extracting the salient features of 2D images formed from an object illuminated by a narrow plane of light. Because a conventional 2D image must be digitized and processed for each profile, current systems do not always provide adequate speed and resolution to meet application demands. To address this challenge, a special purpose image sensor is being developed. Using Compressive Sensing, this sensor will be able to digitize compressed measurements of highly structured images, such as those formed in active 3D scanning, at a rate that would represent the conventional equivalent of 50G pixels/second. It is a significant challenge to process such a high-speed data stream at rates approaching realtime. Therefore, we present a single-chip FPGA design for the extraction of surface profiles from a compressed image stream originating from a 1024 by 768 pixel array at a rate of 14K images per second.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131590468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Memory efficient IP lookup in 100 GBPS networks 100 GBPS网络中内存效率高的IP查找
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645519
J. Matoušek, Martin Skacan, J. Korenek
{"title":"Memory efficient IP lookup in 100 GBPS networks","authors":"J. Matoušek, Martin Skacan, J. Korenek","doi":"10.1109/FPL.2013.6645519","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645519","url":null,"abstract":"The increasing number of devices connected to the Internet together with video on demand have a direct impact to the speed of network links and performance of core routers. To achieve 100 Gbps throughput, core routers have to implement IP lookup in dedicated hardware and represent a forwarding table using a data structure, which fits into the on-chip memory. Current IP lookup algorithms have high memory demands when representing IPv6 prefix sets or introduce very high pre-processing overhead. Therefore, we performed analysis of IPv4 and IPv6 prefixes in forwarding tables and propose a novel memory representation of IP prefix sets, which has very low memory demands. The proposed representation has better memory utilization in comparison to the highly optimized Shape Shifting Trie (SST) algorithm and it is also suitable for IP lookup in 100 Gbps networks, which is shown on a new pipelined hardware architecture with 170 Gbps throughput.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128663100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm 一种定向粗粒度功率门控FPGA开关箱及功率门控感知路由算法
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645548
Chin Hau Hoo, Yajun Ha, Akash Kumar
{"title":"A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm","authors":"Chin Hau Hoo, Yajun Ha, Akash Kumar","doi":"10.1109/FPL.2013.6645548","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645548","url":null,"abstract":"Leakage power has become an important component of the total power consumption in FPGAs as process technology shrinks. In addition, a significant amount of leakage power in FPGAs is consumed by the routing resources. Therefore, leakage power reduction in FPGAs should begin with the routing resources. In this paper, we propose a novel directional coarse-grained power gating architecture for switch boxes. In addition, the existing VPR routing algorithm has been adapted with a new cost function to support the new power gating architecture. Results have shown that the new cost function yields an average improvement of 22% as compared to the existing VPR cost function in terms of the number of power gating regions that can be turned off.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116460688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Altering LUT configuration for wear-out mitigation of FPGA-mapped designs 改变LUT配置以减少fpga映射设计的损耗
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645497
Parthasarathy M. B. Rao, A. Amouri, S. Kiamehr, M. Tahoori
{"title":"Altering LUT configuration for wear-out mitigation of FPGA-mapped designs","authors":"Parthasarathy M. B. Rao, A. Amouri, S. Kiamehr, M. Tahoori","doi":"10.1109/FPL.2013.6645497","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645497","url":null,"abstract":"Bias Temperature Instability (BTI) plays a significant role in transistor aging. As the device dimensions shrink due to technology scaling, this problem poses serious reliability issues. Field Programmable Gate Arrays (FPGAs) use very advanced nano-scaled CMOS technologies, which makes them vulnerable to BTI-induced aging. Previous studies have analyzed the relationship between the configuration of Look-Up Tables (LUTs) and the input signal probabilities against BTI-induced aging of LUTs. In this paper, we propose two methods to mitigate BTI-induced aging in LUTs. The mitigation is performed by manipulating the configuration of the used LUTs and their input signal probabilities, while maintaining the functionality of the mapped design. We implemented the proposed methods using the academic tool Verilog to Routing (VTR). The experimental results show that our methods can mitigate BTI-induced aging of LUT substantially and improve the lifetime of the FPGA-mapped designs, on average, by more than 200%.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127813996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Defect-robust FPGA architectures for intellectual property cores in system LSI 系统LSI中知识产权核的缺陷鲁棒FPGA架构
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645499
M. Amagasaki, Kazuki Inoue, Qian Zhao, M. Iida, M. Kuga, T. Sueyoshi
{"title":"Defect-robust FPGA architectures for intellectual property cores in system LSI","authors":"M. Amagasaki, Kazuki Inoue, Qian Zhao, M. Iida, M. Kuga, T. Sueyoshi","doi":"10.1109/FPL.2013.6645499","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645499","url":null,"abstract":"In this paper, we propose fault-tolerant field-programmable gate array (FPGA) architectures and their computer-aid design (CAD) for intellectual property (IP) cores in system large-scale integration (LSI). Unlike discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The key features of our architectures are regular tile structure, spare modules and bypass wires for fault avoidance, and configuration mechanism for single-cycle reconfiguration. In addition, we develop routing tools, namely EasyRouter for proposed architecture. This tool can handle various array sizes corresponding to developed programmable IP cores. In this evaluation, we compared the performances of conventional FPGA and the proposed fault-tolerant FPGA architectures. On average, our architectures have less than 2.2 times the area and 1.3 times the delay compared with conventional FPGA architectures. At the same time, conventional FP-GAs cannot tolerate faults, whereas our architectures perform with a 90% success rate in fault avoidance for a ratio of faulty tiles of 1% or less.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127841873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Distributed embedded systems design using Petri nets 基于Petri网的分布式嵌入式系统设计
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645617
F. Moutinho, L. Gomes
{"title":"Distributed embedded systems design using Petri nets","authors":"F. Moutinho, L. Gomes","doi":"10.1109/FPL.2013.6645617","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645617","url":null,"abstract":"This paper presents a model-based development approach for distributed embedded systems, supported by design automation tools (available online at http://gres.uninova.pt/). The development approach considers the distributed system specification through a single Petri net model, which includes synchronous components specification and their asynchronous interaction. This specification supports the use of model-checking tools to verify behavioral proprieties and to provide additional information about the required resources to implement the distributed components and their communication channels. The global specification with the additional information supports the use of code generation tools to automatically generate the implementation code (of the synchronous components and communication channels) for software and hardware platforms based on micro-controllers and/or FPGAs.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127985462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Dynamic branch prediction for high-level synthesis 高级综合的动态分支预测
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645540
Vianney Lapôtre, P. Coussy, C. Chavet, Hugues Wouafo, R. Danilo
{"title":"Dynamic branch prediction for high-level synthesis","authors":"Vianney Lapôtre, P. Coussy, C. Chavet, Hugues Wouafo, R. Danilo","doi":"10.1109/FPL.2013.6645540","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645540","url":null,"abstract":"Branch prediction is a widely used technique to optimize performances of pipelined microprocessor architectures. In High-Level Synthesis (HLS) domain, few synthesis techniques for optimizing control flows of data dominated applications have been proposed. Previous works mainly focus on using techniques like path-based scheduling algorithms, speculation techniques or static branch prediction for pipelined loops. In this paper, we present a synthesis flow that combines dynamic branch prediction and operation speculation to remove performance bottlenecks imposed by the control flow of applications. Interest of the proposed approach is shown in term of latency improvements and area overhead through a set of experiments.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127322305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A variation-adaptive retiming method exploiting reconfigurability 一种利用可重构性的自适应变分重定时方法
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645577
Zhenyu Guan, Justin S. J. Wong, S. Chaudhuri, G. Constantinides, P. Cheung
{"title":"A variation-adaptive retiming method exploiting reconfigurability","authors":"Zhenyu Guan, Justin S. J. Wong, S. Chaudhuri, G. Constantinides, P. Cheung","doi":"10.1109/FPL.2013.6645577","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645577","url":null,"abstract":"In this article we present a variation-aware post placement and routing (P&R) retiming method to counteract process variation in FPGAs. Variation-aware retiming takes into account exact variation maps (measured on FPGAs) as opposed to statistical static timing analysis (SSTA) which models process variation with statistical distributions. Experiments are conducted using variation maps measured from 100 Cyclone III FPGAs, and the retiming algorithm is applied using MATLAB. We have shown that for circuits with several retiming choices of equivalent logic depth, up to 30% delay improvement can be achieved for a given variation coefficient of σ/μ = 0.3.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127016430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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