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2013 23rd International Conference on Field programmable Logic and Applications最新文献

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Accelerated FPGA repair through shifted scrubbing 通过移位擦洗加速FPGA修复
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645533
G. Nazar, Leonardo P. Santos, L. Carro
{"title":"Accelerated FPGA repair through shifted scrubbing","authors":"G. Nazar, Leonardo P. Santos, L. Carro","doi":"10.1109/FPL.2013.6645533","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645533","url":null,"abstract":"As critical systems make more and more use of high performance FPGAs, several reliability aspects of these devices come into play. Whenever SRAM-based FPGAs are used, upsets in the configuration memory become a major dependability threat, and must be removed as soon as possible. This is usually accomplished through a process called scrubbing. The traditional scrubbing technique, however, suffers from high energy costs and a long mean time to repair (MTTR). In this work we propose a novel approach to minimize these drawbacks through a triggered shifted scrubbing procedure. The proposed technique exploits the non-uniform distribution of critical bits in the configuration memory of the device to reduce the repair time. It provides an average MTTR reduction of 30% without any changes in the circuit implemented in the FPGA when compared to previous works.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127481944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Fast dynamically updatable packet classifier on FPGA 基于FPGA的快速动态更新分组分类器
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645588
Yun Qu, V. Prasanna
{"title":"Fast dynamically updatable packet classifier on FPGA","authors":"Yun Qu, V. Prasanna","doi":"10.1109/FPL.2013.6645588","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645588","url":null,"abstract":"Packet classification requires multiple fields of the packet header to be matched against entries in a prioritized table; it is still challenging to support dynamic updates for packet classification without sacrificing throughput performance. In this paper, we present a high-throughput pipelined architecture for packet classification on FPGA supporting dynamic updates of the rule set. This architecture is based on Dynamic Bit Vector (Dynamic-BV) approach and supports modify, delete and insert operations during run-time with very little impact on sustained throughput. Experimental results show that, for a 1K rule set on a state-of-the-art FPGA, a throughput of 120 Gbps with 1 million updates/second can be sustained using a single pipeline.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122122557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
FPGA based hardware-software co-designed dynamic binary translation system 基于FPGA的软硬件协同设计动态二进制转换系统
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645554
Yuan Yao, Zhongyong Lu, Qingsong Shi, Wenzhi Chen
{"title":"FPGA based hardware-software co-designed dynamic binary translation system","authors":"Yuan Yao, Zhongyong Lu, Qingsong Shi, Wenzhi Chen","doi":"10.1109/FPL.2013.6645554","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645554","url":null,"abstract":"Binary translation is used to allow applications of one instruction set architecture (ISA) to run on another, thereby maintaining the binary level compatibility across ISAs. Conventional software binary translation systems suffer performance loss because of architectural heterogeneity amongst ISAs, control flow translation and context switches. In this paper, we propose an FPGA based hardware-software co-designed dynamic binary translation (DBT) system, which moderates these issues at a low level of hardware cost. In our DBT system, we propose a MIPS condition code flags register and a modest ISA extension to bridge the architectural gap, a hardware address mapping mechanism to accelerate the handling of control flow instructions, and a scratchpad memory to reduce performance loss during context switches. We implement the system on Xilinx XC5VLX110T. Quantitative experiments reveal that the overall performance improvement is 56.1% over the baseline configuration, with only extra 1.4% of slices and 5.4% of BRAMs of Xilinx XC5VLX110T occupied.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129544372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Design of a multi GBPS Single Carrier digital baseband for 60GHz applications and its FPGA implementation 60GHz多GBPS单载波数字基带设计及FPGA实现
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645573
S. Guntur, F. Jansen, J. Hoogerbrugge, Lotfi Abkari, Eric Vos
{"title":"Design of a multi GBPS Single Carrier digital baseband for 60GHz applications and its FPGA implementation","authors":"S. Guntur, F. Jansen, J. Hoogerbrugge, Lotfi Abkari, Eric Vos","doi":"10.1109/FPL.2013.6645573","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645573","url":null,"abstract":"This paper describes the system architecture, design methodology and subsequent FPGA mapping of a millimeter wave digital baseband for wireless communication in the 60GHz spectral band. The baseband is designed to be compliant with the 802.11ad Single Carrier and Control PHY draft specifications and supports a data rate of 2.5Gbps at the physical layer. The demanding throughput and latency requirements are achieved with a parallel implementation. However, due to limited capacity of the FPGAs present in our prototype platform and complex partitioning requirements, only a scaled down version of the full single carrier baseband that operates at 1/10th the throughput of the specification could be mapped. A minimal real-time hardware MAC was also incorporated and coupled with a 60GHz RF beam-forming front-end to demonstrate file transfer between two independent FPGA prototyping systems. A system throughput of 59Mbps was achieved at the application layer using π/2 QPSK modulation with a 13/16 LDPC code rate.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129162877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
FPGA-based K-means clustering using tree-based data structures 基于fpga的K-means聚类，使用基于树的数据结构
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645501
F. Winterstein, Samuel Bayliss, G. Constantinides
{"title":"FPGA-based K-means clustering using tree-based data structures","authors":"F. Winterstein, Samuel Bayliss, G. Constantinides","doi":"10.1109/FPL.2013.6645501","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645501","url":null,"abstract":"K-means clustering is a popular technique for partitioning a data set into subsets of similar features. Due to their simple control flow and inherent fine-grain parallelism, K-means algorithms are well suited for hardware implementations, such as on field programmable gate arrays (FPGAs), to accelerate the computationally intensive calculation. However, the available hardware resources in massively parallel implementations are easily exhausted for large problem sizes. This paper presents an FPGA implementation of an efficient variant of K-means clustering which prunes the search space using a binary kd-tree data structure to reduce the computational burden. Our implementation uses on-chip dynamic memory allocation to ensure efficient use of memory resources. We describe the trade-off between data-level parallelism and search space reduction at the expense of increased control overhead. A data-sensitive analysis shows that our approach requires up to five times fewer computational FPGA resources than a conventional massively parallel implementation for the same throughput constraint.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130333830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
An event-based middleware for the remote management of runtime hardware reconfiguration 用于远程管理运行时硬件重新配置的基于事件的中间件
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645578
F. Philipp, M. Glesner
{"title":"An event-based middleware for the remote management of runtime hardware reconfiguration","authors":"F. Philipp, M. Glesner","doi":"10.1109/FPL.2013.6645578","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645578","url":null,"abstract":"A procedure to remotely control hardware reconfiguration at runtime is introduced in this paper. Low-level interactions are abstracted by a middleware service that can be called by requests issued by the user or by the underlying operating system. The dynamic loading of hardware modules is managed by a kernel reacting to user-defined events with a customizable scheduling strategy. The system has been designed in a flexible and portable way to support most common runtime reconfiguration approaches and operating systems. Interactions with the middleware are based on commands allowing custom composition and scheduling of hardware modules after deployment. The operation of the middleware is illustrated with the example of a remotely reconfigurable sensor node in a high-performance wireless sensor network.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121676510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Simulation-based HW/SW co-debugging for field-programmable systems-on-chip 基于仿真的现场可编程片上系统软硬件协同调试
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645542
Ruediger Willenberg, P. Chow
{"title":"Simulation-based HW/SW co-debugging for field-programmable systems-on-chip","authors":"Ruediger Willenberg, P. Chow","doi":"10.1109/FPL.2013.6645542","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645542","url":null,"abstract":"We are presenting SimXMD (Simulation-based eXperimental Microprocessor Debugger), a tool that allows developers to debug microcontroller code and custom hardware simultaneously. SimXMD connects a GNU debugger instance to a full-system simulation of an embedded FPGA system. This enables free-roaming investigation of hardware-software interactions inside the system, including reverting back to an earlier point in simulation time. A custom memory logging mechanism enables access to variables in on-chip, off-chip and cached memory. SimXMD is open source, and its modular architecture facilitates extension to other embedded processors as well as different simulators and debuggers.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127690414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Low-cost, high-performance branch predictors for soft processors 用于软处理器的低成本、高性能分支预测器
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645536
Di Wu, Kaveh Aasaraai, Andreas Moshovos
{"title":"Low-cost, high-performance branch predictors for soft processors","authors":"Di Wu, Kaveh Aasaraai, Andreas Moshovos","doi":"10.1109/FPL.2013.6645536","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645536","url":null,"abstract":"This work studies branch predictor implementations for general purpose, pipelined, single core soft processors. It shows that the existing designs do not map well onto reconfigurable hardware since they were optimized for custom logic implementation. This work then proposes an accurate and fast branch predictor that uses few resources on FPGAs. The proposed predictor uses: (1) an FPGA-friendly pattern based direction predictor, (2) a return address stack, (3) in-fetch target address calculation instead of a branch target buffer, and (4) instruction pre-decoding. Experimental measurements using a subset of the SPECCPU2006 workloads show that the presented FPGA-friendly branch predictor delivers high performance while operating at approximately 259 MHz using only 147 ALUTs and one BRAM on an Altera Stratix IV FPGA.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128173066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A secure coprocessor for database applications 用于数据库应用的安全协处理器
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645524
A. Arasu, Ken Eguro, R. Kaushik, Donald Kossmann, Ravishankar Ramamurthy, R. Venkatesan
{"title":"A secure coprocessor for database applications","authors":"A. Arasu, Ken Eguro, R. Kaushik, Donald Kossmann, Ravishankar Ramamurthy, R. Venkatesan","doi":"10.1109/FPL.2013.6645524","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645524","url":null,"abstract":"The scalability and availability of cloud computing makes it an ideal platform for many database applications. However, it is challenging to secure sensitive client information in a practical and rigorous manner against both external attackers and curious cloud administrators. In this paper, we describe a novel secure FPGA-based query coprocessor and discuss how it can be tightly integrated with a commercial database system such as SQL Server. This combination, called Cipherbase, leverages efficient division of labor - using a conventional untrusted cloud server to handle mundane database operations while sensitive data is segregated and processed in trusted hardware to ensure confidentiality. We examine the architectural design issues that affect the achievable performance of the system and report initial results demonstrating the effectiveness for real-world cloud database applications.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130806488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Weasel: A platform-independent streaming-optimized SATA controller Weasel:独立于平台的流优化SATA控制器
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645576
Patrick Lehmann, Thomas Frank, Oliver Knodel, Steffen Köhler, Thomas B. Preußer, R. Spallek
{"title":"Weasel: A platform-independent streaming-optimized SATA controller","authors":"Patrick Lehmann, Thomas Frank, Oliver Knodel, Steffen Köhler, Thomas B. Preußer, R. Spallek","doi":"10.1109/FPL.2013.6645576","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645576","url":null,"abstract":"Field-Programmable Gate Arrays, which are widely used as prototyping platforms, are intruding the domain of custom-specific high-performance hardware accelerators, which operate highly efficiently by exploiting bit- and word-level parallelism. One opportunity to feed these FPGA accelerators with Gbytes of data is the direct attachment of mass-storage devices through a Serial-ATA link. State-of-the-art SATA controllers are designed and optimized for microprocessor-based systems with a random memory access pattern. Our approach, named Weasel, introduces a modularized, platform-independent and streaming-optimized SATA controller, which supports link speeds up to 6 Gbit/s. We demonstrate how to customize the given ATA standard and how to design a generic interface for different vendor-specific multi-gigabit transceivers. Implementations of the platform-independent interface for the Xilinx Virtex-5 and the Altera StratixII GX devices prove our concept. Finally, our measurements using hard-disk and solid-state drives prove a sustained throughput of 540 Mbytes/s over a SATA 6 Gbit/s link achievable. This is close to the theoretical maximum, which is constrained by the attached devices as by the speed of their flash memory.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130926777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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