2013 23rd International Conference on Field programmable Logic and Applications最新文献_第10页

The HercuLeS high-level synthesis environment HercuLeS高级合成环境

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645627

N. Kavvadias, K. Masselos

引用次数: 2

Staticroute: A novel router for the Dynamic Partial Reconfiguration of FPGAS Staticroute:一种用于fpga动态局部重构的新型路由器

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645512

Brahim Al Farisi, Karel Bruneel, D. Stroobandt

引用次数: 9

Titan: Enabling large and complex benchmarks in academic CAD Titan:在学术CAD中支持大型和复杂的基准测试

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645503

Kevin E. Murray, S. Whitty, Suya Liu, J. Luu, Vaughn Betz

{"title":"Titan: Enabling large and complex benchmarks in academic CAD","authors":"Kevin E. Murray, S. Whitty, Suya Liu, J. Luu, Vaughn Betz","doi":"10.1109/FPL.2013.6645503","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645503","url":null,"abstract":"Benchmarks play a key role in FPGA architecture and CAD research, enabling the quantitative comparison of tools and architectures. It is important that these benchmarks reflect modern designs which are large scale systems that make use of heterogeneous resources; however, most current FPGA benchmarks are both small and simple. In this paper we present Titan, a hybrid CAD flow that addresses these issues. The flow uses Altera's Quartus II FPGA CAD software to perform HDL synthesis and a conversion tool to translate the result into the academic BLIF format. Using this flow we created the Titan23 benchmark set, which consists of 23 large (90K-1.8M block) benchmark circuits covering a wide range of application domains. Using the Titan23 benchmarks and a detailed model of Altera's Stratix IV architecture we compared the performance and quality of VPR and Quartus II targeting the same architecture. We found that VPR is at least 2.7× slower, uses 5.1× more memory and 2.6× more wire compared to Quartus II. Finally, we identified that VPR's focus on achieving a dense packing is responsible for a large portion of the wire length gap.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115809223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 94

Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration 基于fpga的TMR电路中基于动态部分重构的有界错误恢复时间研究

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645571

E. Çetin, O. Diessel, Lingkan Gong, Victor Lai

引用次数: 16

FPGA based control for real time systems 基于FPGA的实时系统控制

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645610

Shane T. Fleming, David B. Thomas

{"title":"FPGA based control for real time systems","authors":"Shane T. Fleming, David B. Thomas","doi":"10.1109/FPL.2013.6645610","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645610","url":null,"abstract":"Real time systems must guarantee tasks can be completed by a given deadline. Typically they are designed around the worst case execution time (WCET) of tasks in the system. In general this creates systems with excess slack compared to the average case. Since, real time systems are often embedded devices which are typically battery operated, developing systems with large amounts of slack is undesirable because more slack means more energy usage. There exist scheduling methods that try to adapt to the current environment, for example adaptive reservation scheduling, which assigns a dynamic fraction of the computational resources to each process. However these and more advanced scheduling techniques are rarely adopted in practice due to their high computational overhead. My research hypothesis is that the overheads of complex scheduling and power saving techniques in real time systems can be reduced through developing a coprocessor in the FPGA fabric. Recent developments in reconfigurable device technology include the introduction of new hybrid FPGA/CPU chips, such as the Xilinx Zynq extensible processing platform, where an ARM core is coupled to an FPGA fabric using an AXI bus. By locating the FPGA and CPU on the same die it possible to obtain low-latency power-efficient communication between user logic in the FPGA and tasks on the CPU. This paper presents my preliminary work, which uses a software application with real time deadlines, and creates a controller in the FPGA fabric to dynamically scale the operating frequency of the CPUs, while still guaranteeing that the deadlines can be met. This coprocessor is totally agnostic to the software running on the CPU and provided that some measure of slackness, which is the deadline period subtracted from the execution time, can be obtained it will be able to scale the frequency in a safe manner and reduce dynamic power consumption.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124741133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A novel net-partition-based multithread FPGA routing method 一种新的基于网络分区的多线程FPGA路由方法

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645563

Chun Zhu, Jian Wang, Jinmei Lai

引用次数: 10

Shared memory heterogeneous computation on PCIe-supported platforms 支持pcie的平台上的共享内存异构计算

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645580

S. Shukla, Yang Yang, L. Bhuyan, P. Brisk

引用次数: 8

The study of three-dimensional multiphase-flow simulator 三维多相流模拟器的研究

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645575

Kenta Fujinami, Y. Yamaguchi, Akira Sugiura, Yuetsu Kodama

引用次数: 0

A high-performance overlay architecture for pipelined execution of data flow graphs 一个高性能的覆盖架构，用于数据流图的流水线执行

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645515

D. Capalija, T. Abdelrahman

{"title":"A high-performance overlay architecture for pipelined execution of data flow graphs","authors":"D. Capalija, T. Abdelrahman","doi":"10.1109/FPL.2013.6645515","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645515","url":null,"abstract":"A major issue facing the widespread use of FPGAs as accelerators is their programmability wall: the difficulty of hardware design and the long synthesis times. Overlays-pre-synthesized FPGA circuits that are themselves reconfigurable - promise to tackle these challenges. We design and evaluate an overlay architecture, structured as a mesh of functional units, for pipelined execution of data-flow graphs (DFGs), a common abstraction for expressing parallelism in applications. We use data-driven execution based on elastic pipelines to balance pipeline latencies and achieve a high fMAX, scalability and maximum throughput. We prototype two overlays on a Stratix IV FPGA: a 355 MHz 24×16 integer overlay and a 312 MHz 18×16 floating-point overlay. We also design a tool that maps DFGs to overlays. We map 15 DFGs and show that the two overlays deliver throughputs of up to 35 GOPS and 22 GFLOPS, respectively. We also show that DFG mapping is fast, taking no more than 6 seconds for the largest DFG. Thus, our overlay architecture raises the level of abstraction of FPGA programming closer to that of software and avoids lengthy synthesis time, easing the use of these devices to accelerate applications.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126612795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 79

Radiation mitigation efficiency of scrubbing on the FPGA based CBM-TOF read-out controller 基于FPGA的CBM-TOF读出控制器的擦洗辐射抑制效率

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645532

S. Manz, J. Gebelein, A. Oancea, H. Engel, U. Kebschull

{"title":"Radiation mitigation efficiency of scrubbing on the FPGA based CBM-TOF read-out controller","authors":"S. Manz, J. Gebelein, A. Oancea, H. Engel, U. Kebschull","doi":"10.1109/FPL.2013.6645532","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645532","url":null,"abstract":"Ionizing radiation can severely disturb the function of electronic devices, especially SRAM-based electronics such as Field Programmable Gate Arrays (FPGAs). All components which are being mounted in a radiation environment need to be qualified for use at the respective radiation level. The theory of radiation-induced equipment failures is well known and radiation mitigation techniques have been developed. However, when using commercial off-the-shelf electronics, the internal details of electronic circuits are generally not known. Therefore, the effects of radiation and the efficiency of the mitigation techniques need to be experimentally tested before the usage of the respective electronics can be approved. Here we report the result of such a test, which was carried out at the accelerator facility at Forschungszentrum Jülich, Germany, in August 2012. Contrary to previous tests, our intention was not to characterize the chip's internal logic cells using a test design which optimized for this purpose. We have evaluated the efficiency of the radiation mitigation technique scrubbing on the logic of an actual operational firmware which is currently being used by the Compressed Baryonic Matter collaboration for readout of high-energy physics detector prototypes. We did not use the particle flux as reference for characterizing the efficiency, instead, we directly counted the induced upset rate in the configuration memory of a second identical device in the beam. The firmware itself was running on a Xilinx Virtex-4 FPGA operating directly in a 2 GeV proton beam at a particle rate in the order of some 107s-1cm-2. Scrubbing has increased the lifespan of the design by almost a factor of 50 and reduced the amount of corrupted data by a factor of 200. Considering this result we can approve the usage of an FPGA-based read-out controller for the CBM-ToF subdetector.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128294142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4