Kevin E. Murray, S. Whitty, Suya Liu, J. Luu, Vaughn Betz
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引用次数: 94
摘要
基准测试在FPGA架构和CAD研究中起着关键作用,可以对工具和架构进行定量比较。重要的是,这些基准反映了使用异构资源的大型系统的现代设计;然而,目前大多数的FPGA基准都是小而简单的。在本文中,我们介绍了Titan,一个解决这些问题的混合CAD流。该流程使用Altera的Quartus II FPGA CAD软件执行HDL合成,并使用转换工具将结果转换为学术bif格式。使用此流程,我们创建了Titan23基准测试集,它由23个大型(90K-1.8M块)基准测试电路组成,涵盖了广泛的应用领域。使用Titan23基准测试和Altera的Stratix IV架构的详细模型,我们比较了VPR和Quartus II针对相同架构的性能和质量。我们发现,与Quartus II相比,VPR至少慢2.7倍,使用5.1倍的内存和2.6倍的线路。最后,我们确定VPR的重点是实现密集的包装是电线长度差距的很大一部分。
Titan: Enabling large and complex benchmarks in academic CAD
Benchmarks play a key role in FPGA architecture and CAD research, enabling the quantitative comparison of tools and architectures. It is important that these benchmarks reflect modern designs which are large scale systems that make use of heterogeneous resources; however, most current FPGA benchmarks are both small and simple. In this paper we present Titan, a hybrid CAD flow that addresses these issues. The flow uses Altera's Quartus II FPGA CAD software to perform HDL synthesis and a conversion tool to translate the result into the academic BLIF format. Using this flow we created the Titan23 benchmark set, which consists of 23 large (90K-1.8M block) benchmark circuits covering a wide range of application domains. Using the Titan23 benchmarks and a detailed model of Altera's Stratix IV architecture we compared the performance and quality of VPR and Quartus II targeting the same architecture. We found that VPR is at least 2.7× slower, uses 5.1× more memory and 2.6× more wire compared to Quartus II. Finally, we identified that VPR's focus on achieving a dense packing is responsible for a large portion of the wire length gap.