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2013 23rd International Conference on Field programmable Logic and Applications最新文献

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A self-adaptive image processing application based on evolvable and scalable hardware 基于可进化和可扩展硬件的自适应图像处理应用
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645631
Angel Gallego, J. Mora, A. Otero, B. Lopez, E. D. L. Torre, T. Riesgo
{"title":"A self-adaptive image processing application based on evolvable and scalable hardware","authors":"Angel Gallego, J. Mora, A. Otero, B. Lopez, E. D. L. Torre, T. Riesgo","doi":"10.1109/FPL.2013.6645631","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645631","url":null,"abstract":"Evolvable Hardware (EH) is a technique that consists of using reconfigurable hardware devices whose configuration is controlled by an Evolutionary Algorithm (EA). Our system consists of a fully-FPGA implemented scalable EH platform, where the Reconfigurable processing Core (RC) can adaptively increase or decrease in size. Figure 1 shows the architecture of the proposed System-on-Programmable-Chip (SoPC), consisting of a MicroBlaze processor responsible of controlling the whole system operation, a Reconfiguration Engine (RE), and a Reconfigurable processing Core which is able to change its size in both height and width. This system is used to implement image filters, which are generated autonomously thanks to the evolutionary process. The system is complemented with a camera that enables the usage of the platform for real time applications.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127525133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
SMI: Slack Measurement Insertion for online timing monitoring in FPGAs 用于fpga在线时序监测的松弛测量插入
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645598
Joshua M. Levine, Edward A. Stott, G. Constantinides, P. Cheung
{"title":"SMI: Slack Measurement Insertion for online timing monitoring in FPGAs","authors":"Joshua M. Levine, Edward A. Stott, G. Constantinides, P. Cheung","doi":"10.1109/FPL.2013.6645598","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645598","url":null,"abstract":"Shadow registers, driven by a variable-phase clock, can be used to extract useful timing information from a circuit during operation. This paper presents Slack Measurement Insertion (SMI), an automated tool flow for inserting shadow registers into an FPGA design to enable measurement of timing slack. The flow provides a parameterised level of circuit coverage and results in minimal timing and area overheads. We demonstrate the process through its application to three complex benchmark designs.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121280455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
FPGA IP protection by binding Finite State Machine to Physical Unclonable Function 有限状态机绑定物理不可克隆功能的FPGA IP保护
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645555
Jiliang Zhang, Yaping Lin, Yongqiang Lyu, G. Qu, R. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian
{"title":"FPGA IP protection by binding Finite State Machine to Physical Unclonable Function","authors":"Jiliang Zhang, Yaping Lin, Yongqiang Lyu, G. Qu, R. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian","doi":"10.1109/FPL.2013.6645555","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645555","url":null,"abstract":"In this paper we propose a novel binding mechanism that can protect FPGA IP from being cloned, tampered, or misused; and facilitate the pay-per-use licensing to limit the FPGA IP's execution to specific FPGA devices only. In this mechanism, the FPGA vendors will provide each enrolled device with a Physical Unclonable Function (PUF) that can be deployed securely during fabrication process. The core vendor will embed an augmented Finite State Machine (FSM) into the original FSM structure of the hardware IP (HW-IP) to react on the PUF response to a given challenge. The proposed binding method does not need any Trusted Third Party (TTP) or block cipher for key management and exchange. We analyze several known attacks to hardware IP and show that our method is secure against these attacks. Experimental results on MCNC benchmarks show that the proposed method incurs small design overhead in terms of area, power and delay.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115944088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
RIFFA 2.0: A reusable integration framework for FPGA accelerators RIFFA 2.0: FPGA加速器的可重用集成框架
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645504
Matthew Jacobsen, R. Kastner
{"title":"RIFFA 2.0: A reusable integration framework for FPGA accelerators","authors":"Matthew Jacobsen, R. Kastner","doi":"10.1109/FPL.2013.6645504","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645504","url":null,"abstract":"We present RIFFA 2.0, a reusable integration framework for FPGA accelerators. RIFFA 2.0 provides communication and synchronization for FPGA accelerated applications using simple interfaces for hardware and software. Our goal is to expand the use of FPGAs as an acceleration platform by releasing, as open source, a framework that easily integrates software running on commodity CPUs with FPGA cores. RIFFA 2.0 uses PCIe to connect FPGAs to a CPU's system bus. RIFFA 2.0 extends the original RIFFA project by supporting more classes of Xilinx FPGAs, multiple FPGAs in a system, more PCIe link configurations, higher bandwidth, and Linux and Windows operating systems. This release also supports C/C++, Java, and Python bindings. Tests show that data transfers between hardware and software can saturate the PCIe link to achieve the highest bandwidth possible.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"303 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116267233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 150
A spiking neural network on a portable FPGA tablet 便携式FPGA平板上的脉冲神经网络
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645629
Matthew Naylor, P. Fox, A. T. Markettos, S. Moore
{"title":"A spiking neural network on a portable FPGA tablet","authors":"Matthew Naylor, P. Fox, A. T. Markettos, S. Moore","doi":"10.1109/FPL.2013.6645629","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645629","url":null,"abstract":"We will demonstrate a portable FPGA tablet running a spiking neural network for handwriting recognition. The user draws digits on the tablet's touch-screen, and the neural network performs digit recognition.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116681104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS Field Programmable Analog Array for intelligent sensory application 用于智能传感应用的CMOS现场可编程模拟阵列
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645586
Xiaoyan Cheng, Tao Yin, Qisong Wu, Yiping Jia, Haigang Yang
{"title":"A CMOS Field Programmable Analog Array for intelligent sensory application","authors":"Xiaoyan Cheng, Tao Yin, Qisong Wu, Yiping Jia, Haigang Yang","doi":"10.1109/FPL.2013.6645586","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645586","url":null,"abstract":"A Field-Programmable Analog Array (FPAA) architecture designed for intelligent sensory application is presented, which consists of high performance and high flexible Configurable Analog Blocks (CABs). The CAB is developed to realize both continuous-time and discrete-time circuits for achieving optimal performance in different applications. In addition to employ coarse-grained reconfigurable CAB in FPAA, a fine-grained reconfigurable amplifier in the CAB is utilized to maximize programmability and flexibility. The precision of the analog processing is enhanced by employing fat-tree interconnection network topology to minimize the number of switches used in FPAA and using correlated double sampling (CDS) techniques to suppress the offset and noise. The FPAA is designed and implemented in SMIC 0.18μm CMOS process with a 3.3 V supply voltage. An instrumental amplifier and a capacitive sensor signal readout circuit are taken as application examples. The relative precision and dynamic range of the analog processing are 97.6% and 119dB respectively.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115565346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and FPGA implementation of a 100 Gbit/s optical transport network processor 100gbit /s光传输网络处理器的设计与FPGA实现
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645601
R. Bernardo, Arley H. Salvador, E. Mobilon, L. R. Monte, Stephane Boisclair, Avrum Warshawsky
{"title":"Design and FPGA implementation of a 100 Gbit/s optical transport network processor","authors":"R. Bernardo, Arley H. Salvador, E. Mobilon, L. R. Monte, Stephane Boisclair, Avrum Warshawsky","doi":"10.1109/FPL.2013.6645601","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645601","url":null,"abstract":"This paper presents the design and architecture of an OTN Processor, fully implemented in FPGA devices, that provides transport for Ethernet traffic running at 100 Gbit/s into a long-haul optical network, and regeneration of that OTN signal along the path. In addition to the OTN structure overview, we show how the data are synchronized in the ingress interface, the rate justification and mapping mechanisms, the architecture of the FEC codec, and the FPGAs resource usage. The newest FPGAs allow flexibility and optimal performance for high-speed and high-density designs, as presented in this work. An FPGA platform was used to demonstrate the developed applications in the lab.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"40 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128441499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Weighted partitioning of sequential processing chains for dynamically reconfigurable FPGAS 动态可重构fpga序列处理链的加权划分
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645521
M. Feilen, Andreas Iliopoulos, Michael Vonbun, W. Stechele
{"title":"Weighted partitioning of sequential processing chains for dynamically reconfigurable FPGAS","authors":"M. Feilen, Andreas Iliopoulos, Michael Vonbun, W. Stechele","doi":"10.1109/FPL.2013.6645521","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645521","url":null,"abstract":"Temporal runtime-reconfiguration of FPGAs allows for a resource-efficient sequential execution of signal processing modules. Approaches for partitioning processing chains into modules have been derived in various previous works. We will present a metric for weighted partitioning of pre-defined processing element sequences. The proposed method yields a set of reconfigurable partitions, which are balanced in terms of resources, while jointly have a minimal data throughput. Using this metric, we will formulate a partitioning algorithm with linear complexity and will compare our approach to the state of the art.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132351709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Managing the FPGA memory wall: Custom computing or vector processing? 管理FPGA内存墙:自定义计算或矢量处理?
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645538
Matthew Naylor, P. Fox, A. T. Markettos, S. Moore
{"title":"Managing the FPGA memory wall: Custom computing or vector processing?","authors":"Matthew Naylor, P. Fox, A. T. Markettos, S. Moore","doi":"10.1109/FPL.2013.6645538","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645538","url":null,"abstract":"Managing the memory wall is critical for massively parallel FPGA applications where data-sets are large and external memory must be used. We demonstrate that a soft vector processor can efficiently stream data from external memory whilst running computation in parallel. A non-trivial neural computation case study illustrates that multi-core vector processing coupled with careful layout of data structures performs similarly to an elaborate full-custom memory controller and execution pipeline. The vector processing version was far simpler to code so we encourage others to consider vector machines before contemplating a full-custom architecture on FPGA.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131181359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Aging-based leakage energy reduction in FPGAs fpga中基于老化的泄漏能量降低
2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645562
Sheng Wei, J. Zheng, M. Potkonjak
{"title":"Aging-based leakage energy reduction in FPGAs","authors":"Sheng Wei, J. Zheng, M. Potkonjak","doi":"10.1109/FPL.2013.6645562","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645562","url":null,"abstract":"The presence of process variation (PV) in deep submicron technologies has become a major concern for energy optimization attempts on FPGAs. We develop a negative bias temperature instability (NBTI) aging-based post-silicon leakage energy optimization scheme that stresses the components that are not used or are off the critical paths to reduce the total leakage energy consumption. Furthermore, we obtain the input vectors for aging by formulating the aging objectives into a satisfiability (SAT) problem. We synthesize the low energy design on Xilinx Spartan6 FPGA and evaluate the leakage energy savings on a set of ITC99 and Opencores benchmarks.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128095933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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