Radiation mitigation efficiency of scrubbing on the FPGA based CBM-TOF read-out controller

Abstract

Ionizing radiation can severely disturb the function of electronic devices, especially SRAM-based electronics such as Field Programmable Gate Arrays (FPGAs). All components which are being mounted in a radiation environment need to be qualified for use at the respective radiation level. The theory of radiation-induced equipment failures is well known and radiation mitigation techniques have been developed. However, when using commercial off-the-shelf electronics, the internal details of electronic circuits are generally not known. Therefore, the effects of radiation and the efficiency of the mitigation techniques need to be experimentally tested before the usage of the respective electronics can be approved. Here we report the result of such a test, which was carried out at the accelerator facility at Forschungszentrum Jülich, Germany, in August 2012. Contrary to previous tests, our intention was not to characterize the chip's internal logic cells using a test design which optimized for this purpose. We have evaluated the efficiency of the radiation mitigation technique scrubbing on the logic of an actual operational firmware which is currently being used by the Compressed Baryonic Matter collaboration for readout of high-energy physics detector prototypes. We did not use the particle flux as reference for characterizing the efficiency, instead, we directly counted the induced upset rate in the configuration memory of a second identical device in the beam. The firmware itself was running on a Xilinx Virtex-4 FPGA operating directly in a 2 GeV proton beam at a particle rate in the order of some 107s-1cm-2. Scrubbing has increased the lifespan of the design by almost a factor of 50 and reduced the amount of corrupted data by a factor of 200. Considering this result we can approve the usage of an FPGA-based read-out controller for the CBM-ToF subdetector.