基于高性能lte系统的Femtocell/Macrocell干扰缓解技术的硬件高效实现

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI:10.1109/FPL.2013.6645585

Oriol Font-Bach, N. Bartzoudis, M. Payaró, A. Pascual-Iserte

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引用次数: 2

摘要

本文介绍了一种针对异构多小区lte系统的干扰感知数字前端的FPGA设计。GEDOMIS®测试平台在实际操作条件下实现并验证了资源优化的RTL架构。对联合同步和干扰检测处理块的并行化和并发资源利用进行了底层的详细讨论。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Hardware-efficient implementation of a Femtocell/Macrocell interference-mitigation technique for high-performance LTE-based systems

This paper presents the FPGA design of an interference-aware digital front end tailored for heterogeneous multi-cell LTE-based systems. A resource-optimized RTL architecture has been implemented and validated under realistic operating conditions using the GEDOMIS® testbed. The parallelization and concurrent resource utilization of the joint synchronization and interference detection processing blocks is covered with low-level details.

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2013 23rd International Conference on Field programmable Logic and Applications

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