Altering LUT configuration for wear-out mitigation of FPGA-mapped designs

Abstract

Bias Temperature Instability (BTI) plays a significant role in transistor aging. As the device dimensions shrink due to technology scaling, this problem poses serious reliability issues. Field Programmable Gate Arrays (FPGAs) use very advanced nano-scaled CMOS technologies, which makes them vulnerable to BTI-induced aging. Previous studies have analyzed the relationship between the configuration of Look-Up Tables (LUTs) and the input signal probabilities against BTI-induced aging of LUTs. In this paper, we propose two methods to mitigate BTI-induced aging in LUTs. The mitigation is performed by manipulating the configuration of the used LUTs and their input signal probabilities, while maintaining the functionality of the mapped design. We implemented the proposed methods using the academic tool Verilog to Routing (VTR). The experimental results show that our methods can mitigate BTI-induced aging of LUT substantially and improve the lifetime of the FPGA-mapped designs, on average, by more than 200%.