A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm

Chin Hau Hoo, Yajun Ha, Akash Kumar
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引用次数: 12

Abstract

Leakage power has become an important component of the total power consumption in FPGAs as process technology shrinks. In addition, a significant amount of leakage power in FPGAs is consumed by the routing resources. Therefore, leakage power reduction in FPGAs should begin with the routing resources. In this paper, we propose a novel directional coarse-grained power gating architecture for switch boxes. In addition, the existing VPR routing algorithm has been adapted with a new cost function to support the new power gating architecture. Results have shown that the new cost function yields an average improvement of 22% as compared to the existing VPR cost function in terms of the number of power gating regions that can be turned off.
一种定向粗粒度功率门控FPGA开关箱及功率门控感知路由算法
随着工艺技术的不断缩小,泄漏功率已成为fpga总功耗的重要组成部分。此外,fpga中大量的泄漏功率被路由资源所消耗。因此,fpga的泄漏功率降低应该从路由资源开始。本文提出了一种新颖的开关箱定向粗粒度功率门控结构。此外,现有的VPR路由算法已经适应了一个新的代价函数,以支持新的功率门控架构。结果表明,就可关闭的功率门控区域的数量而言,与现有的VPR成本函数相比,新的成本函数平均提高了22%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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