Vianney Lapôtre, P. Coussy, C. Chavet, Hugues Wouafo, R. Danilo
{"title":"Dynamic branch prediction for high-level synthesis","authors":"Vianney Lapôtre, P. Coussy, C. Chavet, Hugues Wouafo, R. Danilo","doi":"10.1109/FPL.2013.6645540","DOIUrl":null,"url":null,"abstract":"Branch prediction is a widely used technique to optimize performances of pipelined microprocessor architectures. In High-Level Synthesis (HLS) domain, few synthesis techniques for optimizing control flows of data dominated applications have been proposed. Previous works mainly focus on using techniques like path-based scheduling algorithms, speculation techniques or static branch prediction for pipelined loops. In this paper, we present a synthesis flow that combines dynamic branch prediction and operation speculation to remove performance bottlenecks imposed by the control flow of applications. Interest of the proposed approach is shown in term of latency improvements and area overhead through a set of experiments.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 23rd International Conference on Field programmable Logic and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPL.2013.6645540","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Branch prediction is a widely used technique to optimize performances of pipelined microprocessor architectures. In High-Level Synthesis (HLS) domain, few synthesis techniques for optimizing control flows of data dominated applications have been proposed. Previous works mainly focus on using techniques like path-based scheduling algorithms, speculation techniques or static branch prediction for pipelined loops. In this paper, we present a synthesis flow that combines dynamic branch prediction and operation speculation to remove performance bottlenecks imposed by the control flow of applications. Interest of the proposed approach is shown in term of latency improvements and area overhead through a set of experiments.