{"title":"An algorithm for precisely estimating loop-delay in digital predistortion system","authors":"Xiaowei Kong, Zishu He, W. Xia","doi":"10.1109/ICCCAS.2010.5581987","DOIUrl":"https://doi.org/10.1109/ICCCAS.2010.5581987","url":null,"abstract":"In digital predistortion (DPD) design, loop-delay estimation for synchronization is an important work. In this paper, an algorithm for precisely estimating loop-delay in DPD system is proposed. The whole algorithm consists of integer loop-delay estimation and fractional loop-delay estimation. Amplitude-difference correlation function is used to estimate the integer loop-delay estimation. The fractional loop-delay estimation gets the estimate through recursive least squares (RLS) algorithm based on interpolation filter structure. Finally, a series of simulations prove the validity of the algorithm and the effect on the DPD system.","PeriodicalId":199950,"journal":{"name":"2010 International Conference on Communications, Circuits and Systems (ICCCAS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131473353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A unified expression for split-radix DFT algorithms","authors":"G. Bi, Gang Li, Xiumei Li","doi":"10.1109/ICCCAS.2010.5581988","DOIUrl":"https://doi.org/10.1109/ICCCAS.2010.5581988","url":null,"abstract":"This paper presents a unified expression that covers all previously reported split-radix-2/2m, where m is an integer larger than one, algorithms. New split-radix algorithms can be also derived from this unified expression. These algorithms flexibly support DFT sizes N = q · 2r, where q is generally an odd integer. Comparisons show that the computational complexity required by the proposed algorithms for the DFT size N = q · 2r is generally not more than that for the DFT size N = 2r. In particular, our examples show that the split-radix-2/4 algorithm requires a smaller computational complexity compared to other split-radix algorithms and the prime factor algorithms.","PeriodicalId":199950,"journal":{"name":"2010 International Conference on Communications, Circuits and Systems (ICCCAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133577051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new adaptive predistorter based on estimator and LUT","authors":"Zhang Song, Wen Hong, Zhang Gaoyuan, Ren Xiangwei","doi":"10.1109/ICCCAS.2010.5582023","DOIUrl":"https://doi.org/10.1109/ICCCAS.2010.5582023","url":null,"abstract":"The adaptive predistortion is an effective technique to correct the error caused by the nonlinearity of high-power amplifier (HPA). This paper proposes a novel method to construct the adaptive predistorter which combines the estimator and look-up table (LUT) together. The property of the adaptive predistorters depends on the update frequency and algorithm. By setting bit error rate (BER) as an update indicator, update frequency of the new predistorter become significantly low. The update scheme begins when the BER is lower than the standard BER. In the new method, different predistortion algorithms can be chosen according to different input back-off (IBO). Therefore, the calculation amount can be reduced.","PeriodicalId":199950,"journal":{"name":"2010 International Conference on Communications, Circuits and Systems (ICCCAS)","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132279557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"10Gb/s RS-BCH concatenated codec with parallel strategies for fiber communications","authors":"Qingsheng Hu, Chengkun Sun, Hua-An Zhao","doi":"10.1109/ICCCAS.2010.5581992","DOIUrl":"https://doi.org/10.1109/ICCCAS.2010.5581992","url":null,"abstract":"This paper presents a 10Gb/s concatenated RS-BCH code compatible with the protocol of G.975. To achieve the high data rate, parallel technology combining with pipelined strategies are employed. A RS-BCH encoder including 8 RS encoders and 64 BCH encoders is introduced in detail. For the decoder, we present the parallel BCH decoder design in which 8-bit parallel syndrome calculator and Chien search block are adopted. By sharing the key-equation solver, the number of key-equation solver is reduced and the hardware resources are saved. This concatenated codec has been implemented in Xilinx Vertex5 FPGA, and the measurement results show that the data rate of 10Gb/b can be realized under the working frequency of 156MHz.","PeriodicalId":199950,"journal":{"name":"2010 International Conference on Communications, Circuits and Systems (ICCCAS)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127239243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simultaneous functional units and register allocation based power management for high-level synthesis of data-intensive applications","authors":"Feng Wu, N. Xu, Fei Zheng, Fubing Mao","doi":"10.1109/ICCCAS.2010.5581860","DOIUrl":"https://doi.org/10.1109/ICCCAS.2010.5581860","url":null,"abstract":"With the development of fabrication, the capacities of application-specific integrated circuits (ASICs) that implement data-intensive applications are increasing as well. in high-level view, the results of functional units (FUs) and register allocation have a significant impact on power, thermal, area and timing etc., especially for data-dominated behaviors. Techniques for power minimization might be applied in different levels of the design hierarchy, but high-level synthesis (HLS) has attracted a special attention due to its inherent ability of better design space exploration. All kinds of methods for register optimization are presented in the recent past. This paper presents a new simultaneous FUs and register allocation method, which combining heuristic list scheduling algorithm and left-edge algorithm to optimize register number and power. From the experimental results, it shows that different FUs allocation results deliver an average 1.83 reduction in register number. And compared with traditional allocation method, we can obtain a 5.81% reduction in power consumption. In order to optimize area with the design demand, it will be at the expense of power dissipation, our design method also can achieve power-area balance.","PeriodicalId":199950,"journal":{"name":"2010 International Conference on Communications, Circuits and Systems (ICCCAS)","volume":"16 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124309562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Some properties of the Competitive Layer Model with application to object regions extraction","authors":"Bochuan Zheng, Yi Zhang","doi":"10.1109/ICCCAS.2010.5581947","DOIUrl":"https://doi.org/10.1109/ICCCAS.2010.5581947","url":null,"abstract":"It is known that the competitive layer mode (CLM) implemented by Lotka-Volterra recurrent neural networks (LV RNNs) can be used for feature binding. A group of features with similar property can be bound into same layer, however, it is not known which layer a group can be bound to. This is a drawback in some practical applications since it may be required to know which layer a group of features can be bound to. In addition, while using the CLM of LV RNNs for large data set clustering, it is difficult to set appropriate parameters of the network to achieve good clustering results. In this paper, a method called dividing and fixing group method is proposed to overcome this two problems. This method contains two steps. In the first step, it divides a large data set into several small sub data sets with overlapping among neighborhood sub data sets. In the second step, the CLM of LV RNNs is applied to each sub data sets, all features in one group can be bound to same layer by initializing the value of neurons for overlap elements in processing sub data set with the final value of neurons for same elements in processed sub data sets. As one application of this method, it is used to extract object regions in some images.","PeriodicalId":199950,"journal":{"name":"2010 International Conference on Communications, Circuits and Systems (ICCCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123603217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiao Wang, Jinqiao Shi, Longtao He, Li Guo, Qingfeng Tan
{"title":"Analyzing the availability of fast-flux based service network under countermeasures","authors":"Xiao Wang, Jinqiao Shi, Longtao He, Li Guo, Qingfeng Tan","doi":"10.1109/ICCCAS.2010.5582012","DOIUrl":"https://doi.org/10.1109/ICCCAS.2010.5582012","url":null,"abstract":"Fast-flux based service network is first introduced as a technique used to improve the reliability and quality of a service system. But recently, this technique is also adopted by cyber-criminals and Internet miscreants to evade identification and to frustrate law enforcement and anticrime efforts aimed at locating and shutting down the illegal service. Previous work on this topic focuses mostly on detecting and measuring existing fast-flux based service networks ignoring the most import property provided by them—high availability under countermeasures. This paper attacks the availability problem of fast-flux based service network under countermeasures. In this paper, counter-system is taken into account and a model of these networks under countermeasures is presented. Based on this model, two evaluating factors of availability are proposed. By using reliability theory and queuing theory, this paper also performs a study of typical fast-flux based networks and their availability. Results show that both employed strategies and users' network environment have significant impacts on the availability of fast-flux based service network.","PeriodicalId":199950,"journal":{"name":"2010 International Conference on Communications, Circuits and Systems (ICCCAS)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123623001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Theoretical study on coupled multi-layer CRLH transmission lines with specifically designed left-handed shunt inductors","authors":"Y. Horii","doi":"10.1109/ICCCAS.2010.5581894","DOIUrl":"https://doi.org/10.1109/ICCCAS.2010.5581894","url":null,"abstract":"This paper proposes three types of coupled multi-layer composite light-/left-handed transmission lines (TLs) fabricated in parallel beyond a small gap between them. By designing a left-handed shunt inductor appropriately, weakly-coupled TLs (Model 1), differential-mode TLs (Model 2), and tightly-coupled TLs (Model 3) can be realized. Basic behaviour of these TLs are studied theoretically based on even/odd-mode analysis.","PeriodicalId":199950,"journal":{"name":"2010 International Conference on Communications, Circuits and Systems (ICCCAS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123938690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"KUBERA: A security model for Web Applications","authors":"Qiang Wang, Zhiguang Qin","doi":"10.1109/ICCCAS.2010.5581993","DOIUrl":"https://doi.org/10.1109/ICCCAS.2010.5581993","url":null,"abstract":"Web Applications have changed significantly since the World Wide Web was introduced, facing a shift in web content from simple hyperlinked documents to active programs. However, the prevailing web protection model, the same origin policy, is an imperfect approach to identify web applications and govern their behavior. As a result, web applications have become attractive targets of exploitation, especially web plug-ins. In this paper, we present KUBERA, a new web browser security model that adapts lessons from OS to make the browser a more suitable platform for web applications. Using system call interposition, KUBERA is responsible for uniformly specifying and enforcing security policies on not just HTML and JavaScript, but plug-in media and browser extensions as well. We describe our implementation of a prototype of KUBERA, and illustrate how browsers can use KUBERA for securing their resources.","PeriodicalId":199950,"journal":{"name":"2010 International Conference on Communications, Circuits and Systems (ICCCAS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128226971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The self-biased based PLL with fast lock circuit","authors":"Wei Xue-ming, L. Ping","doi":"10.1109/ICCCAS.2010.5581850","DOIUrl":"https://doi.org/10.1109/ICCCAS.2010.5581850","url":null,"abstract":"this paper presents a design of a self-biased based PLL with fast lock circuit, which achieves process technology independence, fixed damping factor, fixed ratio bandwidth related operating frequency, and fast lock time. The lock time of the PLL could be adjusted by demand. The input reference frequency is 125MHz and the PLL generates fixed output frequency of 1250MHz.","PeriodicalId":199950,"journal":{"name":"2010 International Conference on Communications, Circuits and Systems (ICCCAS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127054194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}