{"title":"10Gb/s RS-BCH串联编解码器与并行策略的光纤通信","authors":"Qingsheng Hu, Chengkun Sun, Hua-An Zhao","doi":"10.1109/ICCCAS.2010.5581992","DOIUrl":null,"url":null,"abstract":"This paper presents a 10Gb/s concatenated RS-BCH code compatible with the protocol of G.975. To achieve the high data rate, parallel technology combining with pipelined strategies are employed. A RS-BCH encoder including 8 RS encoders and 64 BCH encoders is introduced in detail. For the decoder, we present the parallel BCH decoder design in which 8-bit parallel syndrome calculator and Chien search block are adopted. By sharing the key-equation solver, the number of key-equation solver is reduced and the hardware resources are saved. This concatenated codec has been implemented in Xilinx Vertex5 FPGA, and the measurement results show that the data rate of 10Gb/b can be realized under the working frequency of 156MHz.","PeriodicalId":199950,"journal":{"name":"2010 International Conference on Communications, Circuits and Systems (ICCCAS)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"10Gb/s RS-BCH concatenated codec with parallel strategies for fiber communications\",\"authors\":\"Qingsheng Hu, Chengkun Sun, Hua-An Zhao\",\"doi\":\"10.1109/ICCCAS.2010.5581992\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 10Gb/s concatenated RS-BCH code compatible with the protocol of G.975. To achieve the high data rate, parallel technology combining with pipelined strategies are employed. A RS-BCH encoder including 8 RS encoders and 64 BCH encoders is introduced in detail. For the decoder, we present the parallel BCH decoder design in which 8-bit parallel syndrome calculator and Chien search block are adopted. By sharing the key-equation solver, the number of key-equation solver is reduced and the hardware resources are saved. This concatenated codec has been implemented in Xilinx Vertex5 FPGA, and the measurement results show that the data rate of 10Gb/b can be realized under the working frequency of 156MHz.\",\"PeriodicalId\":199950,\"journal\":{\"name\":\"2010 International Conference on Communications, Circuits and Systems (ICCCAS)\",\"volume\":\"116 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-07-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Conference on Communications, Circuits and Systems (ICCCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCCAS.2010.5581992\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Communications, Circuits and Systems (ICCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCCAS.2010.5581992","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
10Gb/s RS-BCH concatenated codec with parallel strategies for fiber communications
This paper presents a 10Gb/s concatenated RS-BCH code compatible with the protocol of G.975. To achieve the high data rate, parallel technology combining with pipelined strategies are employed. A RS-BCH encoder including 8 RS encoders and 64 BCH encoders is introduced in detail. For the decoder, we present the parallel BCH decoder design in which 8-bit parallel syndrome calculator and Chien search block are adopted. By sharing the key-equation solver, the number of key-equation solver is reduced and the hardware resources are saved. This concatenated codec has been implemented in Xilinx Vertex5 FPGA, and the measurement results show that the data rate of 10Gb/b can be realized under the working frequency of 156MHz.