ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems最新文献

{"title":"CFD Simulation of Two-Phase Immersion Cooling Using FC-72 Dielectric Fluid","authors":"Amirreza Niazmand, Tushar Chauhan, S. Saini, Pardeep Shahi, Pratik V. Bansode, D. Agonafer","doi":"10.1115/ipack2020-2595","DOIUrl":"https://doi.org/10.1115/ipack2020-2595","url":null,"abstract":"\u0000 With more development in electronics system capable of having larger functional densities, power density is increasing. Immersion cooling demonstrates the highest power usage efficiency (PUE) among all cooling techniques for data centers and there is still interest in optimizing immersion cooling to use it to its full potential. The aim of this paper is to present the effect of inclination and thermal shadowing on two-phase immersion cooling using FC-72. For simulation of boiling, the RPI (Rensselaer Polytechnic Institute) wall boiling model has been used. Also, two empirical models were used for calculation of bubble departure diameter and nucleate site density. The boundary condition was assumed to be constant heat flux and the bath temperature was kept at boiling temperature of FC-72 and the container pressure is assumed to be atmospheric. this study showed that due to the thermal shadowing, boiling boundary layer can lay over the top chipset and increases vapor volume fraction over top chipsets. This ultimately causes increase in maximum temperature of second chip. The other main observation is with higher inclination angle of chip, maximum temperature on the chip decreases up to 3°C.","PeriodicalId":199024,"journal":{"name":"ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116657886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Additive Fabricated Compliant Interconnects: Design, Fabrication and Reliability Effects","authors":"T. Olatunji, D. Huitink","doi":"10.1115/ipack2020-2596","DOIUrl":"https://doi.org/10.1115/ipack2020-2596","url":null,"abstract":"\u0000 Electronics packaging development is greatly dependent on the magnitude of interconnect and on-chip stress that ultimately limits the reliability of electronic components. Thermomechanical strains occur because of the coefficient of thermal expansion mismatch from different conjoined materials being assembled to manufacture a device. To curb the effect of thermal expansion mismatch, studies have been done in integrating compliant structures between dies, solder balls, and substrates. Initial studies have enabled the design and manufacturing of these structures using a photolithography approach which involves an increased number of fabrication steps depending on the complexity of the structures. This current study involves the fabrication of these structures using a different approach, utilizing additive manufacturing that reduces the number of fabrication steps required to obtain compliant geometries, while also providing a platform for unique compliant structures. This paper discusses the method of fabrication and analyzes the properties and effects of these interconnect structures on a die. Structural finite element thermal cycling simulations between −40 to 125°C show about a 115% increase in the solder joint fatigue life. Additionally, fabricated test structures created directly on a PCB were experimentally characterized for compliance using a micro-indenter tester, showing a mechanical compliance range of 265.95 to 656.78 μ/N for selected design parameters to be integrated into a test vehicle.","PeriodicalId":199024,"journal":{"name":"ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122971869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluation of Single Phase Immersion Cooling System for High Performance Server Chassis Using Dielectric Coolants","authors":"Shuai Shao, Tianyi Gao, Huawei Yang, Jie Zhao, Jiajun Zhang","doi":"10.1115/ipack2020-2670","DOIUrl":"https://doi.org/10.1115/ipack2020-2670","url":null,"abstract":"\u0000 Along with advancements in microelectronics packaging, the power density of processor units has steadily increased over time. Data center servers equipped for high performance computing (HPC) often use multiple central processing units (CPUs) and graphical processing units (GPUs), thereby resulting in an increased power density, exceeding 1 kW per U. Many data center organizations are evaluating single phase immersion technology as a potential energy and resource saving cooling option.\u0000 In this work immersion cooling was studied at a power level of 2.7kW/U with a 5U-height immersion cooling tank. Heat generated by a simulated GPU server was transferred to the secondary loop coolant, and then exchanged with the primary loop facility coolant through the heat exchanger. The chiller supply and return temperature and flow rate was controlled for the primary loop.\u0000 The simulated GPU server chassis was designed to provide thermal power equivalent to a high power density server. Eight simulated power heaters, of which each unit was the size of a GPU chipset, was assembled in the comparable location to a real IT equipment on a 4U server chassis. Power for the GPU simulated chassis was able to support up to 2700 W maximum. Three investigations for this immersion cooling system evaluation were performed through comprehensive testing. The first is to identify the key decision making factor(s) for evaluating the thermal performance of 4 hydrocarbon-based dielectric coolants, including power parametric analysis, transient analysis, power cycling test, and fluid temperature profiling. The second is to develop an optimization strategy for the immersion system thermal performance. The third is to verify the capability of an 1U heat sink to support high density processor units over 300 W per GPU in an immersion cooling solution.","PeriodicalId":199024,"journal":{"name":"ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123610142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of Accelerated Degradation Test Method and Failure Analysis of Flexible Hybrid Electronic Devices","authors":"Alex Davila-Frias, V. Marinov, O. Yadav, Y. Atanasov","doi":"10.1115/ipack2020-2525","DOIUrl":"https://doi.org/10.1115/ipack2020-2525","url":null,"abstract":"\u0000 Accelerated life testing (ALT) has been a common choice to study the effects of environmental stresses on flexible hybrid electronics (FHE), a promising technology to produce flexible electronic devices. Nevertheless, accelerated degradation testing (ADT) has proven to be a more effective approach, which does not require failure occurrences, allowing shorter testing times. Since FHE devices are expected to be highly reliable, ADT provides useful information in the form of degradation data for further analysis without actual failure data. In this paper, we present the design and experimental setup of ADT for FHE considering two stress factors simultaneously. We use daisy-chain resistance as a measurable degradation characteristic to periodically monitor the degradation of FHE products under accelerated stress conditions. Two stress factors, temperature and humidity, are considered and ADT was carried out considering four combinations of temperature and humidity simultaneously. Failure analysis was performed on failed units to investigate the failure process and location of the failure. The ADT data was used to fit in the appropriate mathematical degradation model representing the failure process. The data analysis showed faster degradation paths for higher stress combinations. Finally, we present insights and further research opportunities to expand the work.","PeriodicalId":199024,"journal":{"name":"ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130015567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Correlation of Microstructural Evolution With the Dynamic-Mechanical Viscoelastic Properties of Underfill Under Sustained High Temperature Operation","authors":"P. Lall, Madhu L. Kasturi, Haotian Wu, Edward W. Davis, J. Suhling","doi":"10.1115/ipack2020-2675","DOIUrl":"https://doi.org/10.1115/ipack2020-2675","url":null,"abstract":"\u0000 Automotive underhood electronics are subjected to high operating temperatures in the neighborhood of 150 to 200°C for prolonged periods in the neighborhood of 10-years. Consumer grade off-the shelf electronics are designed to operate at 55 to 85 °C with a lower use-life of 3 to 5 years. Underfill materials are used to provide supplemental restraint to fine-pitch area array electronics and meet the reliability requirements. In this paper, a number of different underfill materials are subjected to automotive underhood temperatures to study the effect of long time isothermal exposure on microstructure and dynamic-mechanical properties. It has been shown that isothermal aging oxidizes the underfill, which can change the mechanical properties of the material significantly. The oxidation of underfill was studied experimentally by measuring oxidation layer thickness using polarized optical microscope. The effect on the mechanical properties was studied using the dynamic mechanical properties of underfill with DMA (Dynamic Mechanical Analyzer). Two different underfill materials were subjected to three different isothermal exposure, which are below, near and above the glass transition temperature of the underfills. The dynamic mechanical viscoelastic properties like storage modulus, loss modulus, tan delta and their respective glass transition temperatures were investigated. Three point bending mode was used in the DMA with a frequency of 1 Hz operating at 3 °C/min.","PeriodicalId":199024,"journal":{"name":"ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134244973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multifunctional Magnetic Nanocomposite Encapsulant for EMI Shielding in Power Electronics","authors":"Hayden Carlton, A. Iradukunda, D. Huitink, Sarah Myane, Noah Akey, Asif Imran, Fang Luo","doi":"10.1115/ipack2020-2576","DOIUrl":"https://doi.org/10.1115/ipack2020-2576","url":null,"abstract":"\u0000 As power densities and switching frequencies dramatically increase, a potential area of advancement for encapsulant technologies is to utilize them to mitigate electromagnetic interference, which directly impacts device efficiency at high switching frequencies; one promising topic involves the creation of magnetic nanoparticle-enhanced encapsulants, with intrinsic sensitivity to electromagnetic fields that could provide additional noise shielding for power electronic devices. A nanocomposite encapsulant was created by directly incorporating magnetic iron oxide nanoparticles into a silicone matrix. The nanoparticles, with an average size of 100 nm, achieved excellent dispersion in the silicone polymer, even at high concentrations, with no additive or surfactants needed to improve stability. Material testing, including thermo mechanical analysis and thermal conductivity measurements were performed to determine if the addition of the nanoparticles altered the thermal or mechanical properties of the base silicone. The nanocomposites at different concentrations observed thermal conductivities of 0.5 W/m-K and coefficient of thermal expansions of 280 ppm/°C, which resembles that of normal silicone; however, the addition of the iron oxide reduced the dielectric breakdown strength of the silicone matrix exponentially with respect to concentration from 20 kV/mm to 3 kV/mm. Further efforts to optimize the dielectric properties of the nanocomposites with respect to the nanoparticle loading is necessary in order to directly apply this technology; however, the results indicate magnetic nanocomposites could be a potential avenue towards mitigating electromagnetic interference in power devices.","PeriodicalId":199024,"journal":{"name":"ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131957662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Material Impact With Package Solution for 5G RF Application","authors":"Po Yuan Su, Yu Po Wang, Pai Yu Cheng, Y. Lu, Teny Shih, Andrew Kang, David Lai, D. Jiang","doi":"10.1115/ipack2020-2507","DOIUrl":"https://doi.org/10.1115/ipack2020-2507","url":null,"abstract":"\u0000 From the fifth-generation (5G) of system architecture evolution, there are more and more demands which require high data rate communication, low latency, and massive connectivity for network data transmission. For millimeter-wave (mm-wave), communications, the antenna size for mobile application is shunk from PCB level to package level, therefore Antenna in Package (AiP) is developed.\u0000 Recently, high bandwidth with high performance data rate transmission is the key for 5G and that also can provide the lower latency than current fourth generation. That is the reason can be explained that millimeter-wave (mm-wave) of bandwidth can offer excellent network coverage in the city and the antenna design for 5G wireless telcommcation is getting important. All frequency of signal have to use the networking devices to achieve high speed data transmission requirement. As we known, mm-wave is used for mobile phone of signal transmission, and the material with the package design become really important. The mm-wave performance can be impacted by material with structure design, and DK, DF and package level design will be the material portion to effect the signal performance.\u0000 In this paper, material selection, antenna array and package design will be the key for the Antenna in Package (AiP). For antenna design, we need the lower DF, DK, phase array and structure design to help our signal performance which means lowest insertion loss will be the best for signal transmission. We will do the comparsion for the paper discussion for the material, package and beamforming with antenna array design. Finally, this paper will provide the advanced package solution for future application.","PeriodicalId":199024,"journal":{"name":"ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133854540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Partitioned Heat Sinks for Improved Natural Convection","authors":"T. Salamon, R. Kempers, Brian A. Lynch, K. Terrell, Elina Simon","doi":"10.1115/ipack2020-2553","DOIUrl":"https://doi.org/10.1115/ipack2020-2553","url":null,"abstract":"\u0000 The main drivers contributing to the continued growth of network traffic include video, mobile broadband and machine-to-machine communication (Internet of Things, cloud computing, etc.). Two primary technologies that next-generation (5G) networks are using to increase capacity to meet these future demands are massive MIMO (Multi-Input Multi-Output) antenna arrays and new frequency spectrum. The massive MIMO antenna arrays have significant thermal challenges due to the presence of large arrays of active antenna elements coupled with a reliance on natural convection cooling using vertical plate-finned heat sinks. The geometry of vertical plate-finned heat sinks can be optimized (for example, by choosing the fin pitch and thickness that minimize the thermal resistance of the heat sink to ambient air) and enhanced (for example, by embedding heat pipes within the base to improve heat spreading) to improve convective heat transfer. However, heat transfer performance often suffers as the sensible heat rise of the air flowing through the heat sink can be significant, particularly near the top of the heat sink; this issue can be especially problematic for the relatively large or high-aspect-ratio heat sinks associated with massive MIMO arrays. In this study a vertical plate-finned natural convection heat sink was modified by partitioning the heat sink along its length into distinct sections, where each partitioned section ejects heated air and entrains cooler air. This approach increases overall heat sink effectiveness as the net sensible heat rise of the air in any partitioned section is less than that observed in the unpartitioned heat sink. Experiments were performed using a standard heat sink and equivalent heat sinks partitioned into two and three sections for the cases of ducted and un-ducted natural convection with a uniform heat load applied to the rear of the heat sink. Numerical models were developed which compare well to the experimental results and observed trends. The numerical models also provide additional insight regarding the airflow and thermal performance of the partitioned heat sinks. The combined experimental and numerical results show that for relatively tall natural convection cooled heat sinks, the partitioning approach significantly improves convective heat transfer and overall heat sink effectiveness.","PeriodicalId":199024,"journal":{"name":"ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"368 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114529565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation Regarding Thermal Resistance of Surface Mount Type Discrete Power Semiconductor Package","authors":"K. Nishi","doi":"10.1115/ipack2020-2631","DOIUrl":"https://doi.org/10.1115/ipack2020-2631","url":null,"abstract":"\u0000 Power electronics is becoming more important than before with motor application expansion. For size reduction of inverter integrated motor design, accurate temperature prediction of power devices is becoming critical. For up to several hundred-watt motor system, inverter is designed with discrete power devices with standard package. This paper investigates package thermal resistance of a DPAK package as an example. Firstly, three-dimensional heat conduction simulation only with DPAK package model is conducted. It is found that its package thermal resistance changes by ∼6.2°C/W due to boundary condition variation. After that, simulation not only with DPAK package but also with PCB is conducted to understand package thermal resistance of a real system implementation case. It is found that package thermal resistance varies drastically by copper trace size. “Smallest” case with minimum copper traces shows ∼0.9 °C/W higher value than larger copper trace case and shows ∼1.5 °C/W higher value than the case that copper trace fully covers PCB top surface, in the case that horizontal PCB size is 50 × 50 mm.\u0000 After that, two types of test boards with different trace size for of n-channel MOSFET with DPAK package are prepared. Measurements are conducted to know package thermal resistance variation by copper trace size. Transient thermal impedance curve is obtained from measurement result and is converted to a cumulative Rth-Cth curve to know and discuss the difference by copper trace size of these two test boards. The difference is also discussed with and compared to that of simulation results.","PeriodicalId":199024,"journal":{"name":"ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116587654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CFD Analysis on Liquid Cooled Cold Plate Using Copper Nanoparticles","authors":"Pardeep Shahi, Sarthak Agarwal, S. Saini, Amirreza Niazmand, Pratik V. Bansode, D. Agonafer","doi":"10.1115/ipack2020-2592","DOIUrl":"https://doi.org/10.1115/ipack2020-2592","url":null,"abstract":"\u0000 In today’s world, most data centers have multiple racks with numerous servers in each of them. The high amount of heat dissipation has become the largest server-level cooling problem for the data centers. The higher dissipation required, the higher is the total energy required to run the data center. Although still the most widely used cooling methodology, air cooling has reached its cooling capabilities especially for High-Performance Computing data centers. Liquid-cooled servers have several advantages over their air-cooled counterparts, primarily of which are high thermal mass, lower maintenance. Nano-fluids have been used in the past for improving the thermal efficiency of traditional dielectric coolants in the power electronics and automotive industry. Nanofluids have shown great promise in improving the convective heat transfer properties of the coolants due to a proven increase in thermal conductivity and specific heat capacity.\u0000 The present research investigates the thermal enhancement of the performance of de-ionized water-based dielectric coolant with Copper nanoparticles for a higher heat transfer from the server cold plates. Detailed 3-D modeling of a commercial cold plate is completed and the CFD analysis is done in a commercially available CFD code ANSYS CFX. The obtained results compare the improvement in heat transfer due to improvement in coolant properties with data available in the literature.","PeriodicalId":199024,"journal":{"name":"ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126183259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}