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ESSCIRC '88: Fourteenth European Solid-State Circuits Conference最新文献

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Realization of Conditional-Sum Adders With Low Latency Time 低延时条件和加法器的实现
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468258
A. Rothermel, B. Hosticka, G. Troster, J. Arndt
{"title":"Realization of Conditional-Sum Adders With Low Latency Time","authors":"A. Rothermel, B. Hosticka, G. Troster, J. Arndt","doi":"10.1109/ESSCIRC.1988.5468258","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468258","url":null,"abstract":"Conditional-sum adders have been realized in a standard 2.5 ¿m CMOS technology. These adders offer short propagation delay and latency time (12.5 ns for 32 bit addition) and consume only moderate chip area (i.e. 80 × 460 ¿m2 for one bit in a 32 bit adder). The adders have been realized with CMOS transmission-gates. They allow static operation and consume only dynamic power (like standard CMOS). The layout exhibits high regularity and can be easily adjusted to various word-lengths.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131578361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A High Precision PCM Codec Using Sigma-Delta Modulation 采用Sigma-Delta调制的高精度PCM编解码器
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468467
V. Friedman, D.-P. Chen, E. Fields, J. Scott, T. R. Viswanathan
{"title":"A High Precision PCM Codec Using Sigma-Delta Modulation","authors":"V. Friedman, D.-P. Chen, E. Fields, J. Scott, T. R. Viswanathan","doi":"10.1109/ESSCIRC.1988.5468467","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468467","url":null,"abstract":"","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131988224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-Voltage High-Drive Differential Amplifier For ISDN Applications 一种用于ISDN应用的低压高驱动差分放大器
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468327
L. Tomasini, A. Gola, R. Castello
{"title":"A Low-Voltage High-Drive Differential Amplifier For ISDN Applications","authors":"L. Tomasini, A. Gola, R. Castello","doi":"10.1109/ESSCIRC.1988.5468327","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468327","url":null,"abstract":"A CMOS differential buffer amplifier for ISDN applications is reported. The chip operates from a single 5 V power supply and can deliver a 6 Vpp 80 kHz signal into a load of 100 ohm and/or 300 pF with a THD of about 0.25 %. The circuit main feature is its PSRR which remain practically constant from de to several hundred kHz around - 75 dB for both positive and negative supplies with the common mode voltage generated ou chip. The step response at 1 % for the same loading conditions is less than 500 nsec for a step of + 1.5V and less than 1 ¿sec for a step of ++6V. By using relatively small devices at the output the amplifier occupies an area of only 1720 square mils in a 2.5 ¿m n-well CMOS technology.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130615518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Switched Capacitor "Neural" Networks for Quadratic Programming 二次规划的开关电容“神经”网络
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468257
A. Rueda, Angel Rtodrguez-Vazquez, J. Huertas, R. Domínguez-Castro
{"title":"Switched Capacitor \"Neural\" Networks for Quadratic Programming","authors":"A. Rueda, Angel Rtodrguez-Vazquez, J. Huertas, R. Domínguez-Castro","doi":"10.1109/ESSCIRC.1988.5468257","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468257","url":null,"abstract":"A circuit for on-line solving of quadratic programming problems is presented. The circuit is made using switched-capacitor techniques thus being adequate for monolithic implementation. Simulation results using a mixed-mode simulator (DIANA) for CMOS implementations of different problems are included illustrating the validity of the approach. Finally, the connection between the proposed circuit and analog neural networks is also outlined.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127020134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Integrated Circuits Digital Network (ISDN) 集成电路数字网(ISDN)
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/esscirc.1988.5468346
J. Kam
{"title":"Integrated Circuits Digital Network (ISDN)","authors":"J. Kam","doi":"10.1109/esscirc.1988.5468346","DOIUrl":"https://doi.org/10.1109/esscirc.1988.5468346","url":null,"abstract":"","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126796999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Broadband Amplifier using GaAs/GaAlAs HBTs 基于GaAs/GaAlAs的宽带放大器
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468367
P. Topham, A. Long, P. Saul, J. G. Parton, B. A. Hollis, N. A. Hiams, R. Hayes, R. Goodfellow
{"title":"A Broadband Amplifier using GaAs/GaAlAs HBTs","authors":"P. Topham, A. Long, P. Saul, J. G. Parton, B. A. Hollis, N. A. Hiams, R. Hayes, R. Goodfellow","doi":"10.1109/ESSCIRC.1988.5468367","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468367","url":null,"abstract":"","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115214225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Architecture and Design Methodology of 32KByte Integrated Cache Memory 32KByte集成高速缓存的体系结构与设计方法
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468419
K. Nogami, T. Sakurai, K. Sawada, T. Shirotori, T. Takayanagi, T. Iizuka, T. Maeda, J. Matsunaga, H. Fuji, K. Maeguchi, K. Kobayashi, T. Ando, Yoshiki Hayakashi, A. Miyoshi, Kazuyuki Sato
{"title":"Architecture and Design Methodology of 32KByte Integrated Cache Memory","authors":"K. Nogami, T. Sakurai, K. Sawada, T. Shirotori, T. Takayanagi, T. Iizuka, T. Maeda, J. Matsunaga, H. Fuji, K. Maeguchi, K. Kobayashi, T. Ando, Yoshiki Hayakashi, A. Miyoshi, Kazuyuki Sato","doi":"10.1109/ESSCIRC.1988.5468419","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468419","url":null,"abstract":"The architectural aspects of a newly deveoped integrated cache memory is described in this paper, which includes 32Kbyte DATA memory with a typical ADDRESS to HIT delay, the largest memory size and fastest speed ever reported as an integrated cache memory[1]. The device integrates data/instruction memory, tag memory and a comparator on a chip. It serves as a cache memory of several host MPUs by aluminum masterslice.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124782574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Floating CMOS Bandgap Voltage Reference For Differential Applications 差分应用的浮动CMOS带隙基准电压
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468337
M. Ferro, F. Salerno, Rinaldo Castello
{"title":"A Floating CMOS Bandgap Voltage Reference For Differential Applications","authors":"M. Ferro, F. Salerno, Rinaldo Castello","doi":"10.1109/ESSCIRC.1988.5468337","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468337","url":null,"abstract":"The first floating CMOS bandgap voltage reference is presented. The circuit is very suitable for precision applications in fully differential analog circuits. lt generates a continuous time low impedance voltage of 2.48V ± 24 mV before trimming. The experimental prototype occupies 1800 mils square and dissipates 6 mW with a single supply voltage of 5V. Temperature stability is better than 20 ppm/C over a temperature range from 0 to 100 degree. The measured high frequency power supply rejection of-50 dB at 100KHz is the best ever reported.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"439 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123611689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
High Speed, Large Bandwidth Operational Amplifier Resulting from a Mixed Technology Approach 基于混合技术的高速大带宽运算放大器
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468331
A. Gola
{"title":"High Speed, Large Bandwidth Operational Amplifier Resulting from a Mixed Technology Approach","authors":"A. Gola","doi":"10.1109/ESSCIRC.1988.5468331","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468331","url":null,"abstract":"A recently developed mixed technology which combines high cut-off frequency bipolar transistors with 2¿m CMOS allows improved circuit design of both linear and digital circuits.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121059645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Flip-Flop Sensor Array with On-Spot A/D Conversion 具有现场A/D转换的触发器传感器阵列
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468270
S. Wouters, W. Lian
{"title":"A Flip-Flop Sensor Array with On-Spot A/D Conversion","authors":"S. Wouters, W. Lian","doi":"10.1109/ESSCIRC.1988.5468270","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468270","url":null,"abstract":"A two dimensional optical flip-flop sensor array is presented. It consists of 64 flip-flop sensors, each of which contains two phototransistors with different light sensitivity. Each flip-flop sensor senses the light intensity and converts it to a series of \"one\" s and \"zero\"s. It is operated by turning on and off the supply current with a high frequency. During absence of light the flip-flop is totally symmetrical and as a result the number of \"one\"s and \"zero\"s is equal. Light causes an asymmetry in the flip-flop that changes the ratio of \"one\"s and \"zero\"s. A fully digital output is obtained by counting the number of \"one\"s. A triangle wave voltage is applied to the flip-flop in order to vary the threshold of the flip-flop. The device showed that a large array of sensors with on-spot A/D conversion can be realized using the flip-flop sensor technique.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125746841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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