Realization of Conditional-Sum Adders With Low Latency Time

Abstract

Conditional-sum adders have been realized in a standard 2.5 ¿m CMOS technology. These adders offer short propagation delay and latency time (12.5 ns for 32 bit addition) and consume only moderate chip area (i.e. 80 × 460 ¿m2 for one bit in a 32 bit adder). The adders have been realized with CMOS transmission-gates. They allow static operation and consume only dynamic power (like standard CMOS). The layout exhibits high regularity and can be easily adjusted to various word-lengths.