{"title":"低延时条件和加法器的实现","authors":"A. Rothermel, B. Hosticka, G. Troster, J. Arndt","doi":"10.1109/ESSCIRC.1988.5468258","DOIUrl":null,"url":null,"abstract":"Conditional-sum adders have been realized in a standard 2.5 ¿m CMOS technology. These adders offer short propagation delay and latency time (12.5 ns for 32 bit addition) and consume only moderate chip area (i.e. 80 × 460 ¿m2 for one bit in a 32 bit adder). The adders have been realized with CMOS transmission-gates. They allow static operation and consume only dynamic power (like standard CMOS). The layout exhibits high regularity and can be easily adjusted to various word-lengths.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Realization of Conditional-Sum Adders With Low Latency Time\",\"authors\":\"A. Rothermel, B. Hosticka, G. Troster, J. Arndt\",\"doi\":\"10.1109/ESSCIRC.1988.5468258\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Conditional-sum adders have been realized in a standard 2.5 ¿m CMOS technology. These adders offer short propagation delay and latency time (12.5 ns for 32 bit addition) and consume only moderate chip area (i.e. 80 × 460 ¿m2 for one bit in a 32 bit adder). The adders have been realized with CMOS transmission-gates. They allow static operation and consume only dynamic power (like standard CMOS). The layout exhibits high regularity and can be easily adjusted to various word-lengths.\",\"PeriodicalId\":197244,\"journal\":{\"name\":\"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1988.5468258\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1988.5468258","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
条件和加法器已在标准的2.5 m CMOS技术中实现。这些加法器提供较短的传播延迟和延迟时间(32位加法12.5 ns)，并且仅消耗适度的芯片面积(即32位加法器中每位80 × 460¿m2)。加法器是用CMOS传输门实现的。它们允许静态操作，只消耗动态功率(如标准CMOS)。布局具有高度的规律性，可以很容易地调整到不同的字长。
Realization of Conditional-Sum Adders With Low Latency Time
Conditional-sum adders have been realized in a standard 2.5 ¿m CMOS technology. These adders offer short propagation delay and latency time (12.5 ns for 32 bit addition) and consume only moderate chip area (i.e. 80 × 460 ¿m2 for one bit in a 32 bit adder). The adders have been realized with CMOS transmission-gates. They allow static operation and consume only dynamic power (like standard CMOS). The layout exhibits high regularity and can be easily adjusted to various word-lengths.
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