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An Over-The-Cell Router over - cell路由器
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804509
D. Deutsch, P. Glick
{"title":"An Over-The-Cell Router","authors":"D. Deutsch, P. Glick","doi":"10.1145/800139.804509","DOIUrl":"https://doi.org/10.1145/800139.804509","url":null,"abstract":"A program that produces single-layer planar routing over the cells for I2L and LST2L logic arrays is described. This router has been integrated into a layout system which was previously restricted to the layout of standard cell LSI chips. When used in conjunction with a channel router, the complete routing is produced automatically. This paper defines the over-the-cell routing problem, describes the algorithms for its solution, and presents typical routing results.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121285283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
The Use of Graphics Processors for Circuit Design Simulation at GTE AE Labs 图形处理器在GTE AE实验室电路设计仿真中的应用
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804568
J. Dyer, A. Laha, Ernest J. Moran, W. Smart
{"title":"The Use of Graphics Processors for Circuit Design Simulation at GTE AE Labs","authors":"J. Dyer, A. Laha, Ernest J. Moran, W. Smart","doi":"10.1145/800139.804568","DOIUrl":"https://doi.org/10.1145/800139.804568","url":null,"abstract":"Design and test engineers in some companies have resisted the use of circuit simulation programs because of the necessity of learning a special language for circuit input and of the necessity of becoming too involved in computer operations. To overcome these objections the Circuit Analysis and Simulation Group at AE Labs has designed graphics processor programs to interface between the designer and the simulation programs. This paper provides a description of the current generation of these programs.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122883782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Automatic Design with Dependence Graphs 依赖图的自动设计
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804575
A. Casavant, D. Gajski, D. Kuck
{"title":"Automatic Design with Dependence Graphs","authors":"A. Casavant, D. Gajski, D. Kuck","doi":"10.1145/800139.804575","DOIUrl":"https://doi.org/10.1145/800139.804575","url":null,"abstract":"A design automation system for the design of digital systems from a high-level algorithmic description is proposed. The definition of the data-dependence graph and techniques for performing transformations that lead to optimization of hardware are described. The system can be used on several levels of design with the VLSI layout level given particular emphasis.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121415568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Methods for Generalized Deductive Fault Simulation 广义演绎故障模拟方法
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804560
N. Giambiasi, A. Miara, D. Muriach
{"title":"Methods for Generalized Deductive Fault Simulation","authors":"N. Giambiasi, A. Miara, D. Muriach","doi":"10.1145/800139.804560","DOIUrl":"https://doi.org/10.1145/800139.804560","url":null,"abstract":"In this paper, the authors describe methods for generalized deductive fault simulation of digital networks. By introducing the notion of unknown fault list, the propagation algorithm through gates modelized with rise and fall times are simplified with the same accuracy.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129138368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
COMET - A Fast Component Placer COMET -一个快速组件研磨机
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804571
V. Smith, Robert J. Smith, Phil A. Preston
{"title":"COMET - A Fast Component Placer","authors":"V. Smith, Robert J. Smith, Phil A. Preston","doi":"10.1145/800139.804571","DOIUrl":"https://doi.org/10.1145/800139.804571","url":null,"abstract":"Classical Unconnected Set (UCS) and other iterative placement improvement algorithms may converge slowly toward desirable component arrangements. This paper discusses mechanisms that inhibit convergence, then proposes techniques for accelerating rate of improvement. A placer incorporating these procedures is described, and experimental results demonstrating effectiveness of the approach are given.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114263038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Detecting Bridging and Stuck-At Faults at Input and Output Pins of Standard Digital Components 标准数字元件输入输出引脚桥接和卡死故障检测
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804574
M. Karpovsky, S. Su
{"title":"Detecting Bridging and Stuck-At Faults at Input and Output Pins of Standard Digital Components","authors":"M. Karpovsky, S. Su","doi":"10.1145/800139.804574","DOIUrl":"https://doi.org/10.1145/800139.804574","url":null,"abstract":"Due to the advances in the integrated circuit technology, there is an increasing importance in testing bridging (short circuit) failures in digital networks. Unfortunately, very little work has been done in this area. This paper presents the schemes for the detection of feedback bridgings between the inputs and outputs through the observation of oscillation and asynchronous behavior of sequential networks created by bridging faults. The lower and upper bounds on the number of tests for detecting all feedback bridging faults are given. Conditions for the undetectability of input bridgings are given and a method for testing input bridgings is presented. The results are generalized to detect bridging and stuck-at faults in the input and output lines of a multiple-output network. Finally, the complete test sets are given for detecting input, output and feedback bridgings as well as stuck-at faults at the input and output pins of the standard integrated circuit chips including shift registers, counters, decoders, multiplexers, adders/subtracters, multipliers, dividers and RAM. Future unsolved problems in this area are also given.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114575420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Design Automation at a Large Architect-Engineer 大型架构工程师的设计自动化
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804510
E. Chelotti, D. P. Bossie
{"title":"Design Automation at a Large Architect-Engineer","authors":"E. Chelotti, D. P. Bossie","doi":"10.1145/800139.804510","DOIUrl":"https://doi.org/10.1145/800139.804510","url":null,"abstract":"Gibbs & Hill (G&H) has been a proponent, developer, and user of Design Automation (DA) techniques for over fifteen years. Progression has been steady and significant, beginning with the use of relatively simple batch computer programs for the solution of specific engineering problems to the current broad application of state-of-the-art hardware and software including interactive graphics and data base management systems. This progress has been matched by acceptance, and at G&H DA is considered a normal and viable mode of operation rather than an alternate method subject to doubts by management, clients, and personnel. The Design Automation objective is an on-line, integrated data base approach to all aspects and phases of our work, ranging from conceptual design to construction management. The cornerstone of the Design Automation system is CADAEsm (Computer Aided Design and Engineering) which is an Interactive graphics system that is used to produce design drawings, including both dimensional and nondimensional. The G&H Design Automation system is developed, refined, and maintained by a dedicated staff of DA professionals.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115722966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Algebraic Analysis of Nondeterministic Behavior 不确定性行为的代数分析
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804573
Sany M. Leinwand, T. Lamdan
{"title":"Algebraic Analysis of Nondeterministic Behavior","authors":"Sany M. Leinwand, T. Lamdan","doi":"10.1145/800139.804573","DOIUrl":"https://doi.org/10.1145/800139.804573","url":null,"abstract":"This paper is concerned with the analysis of design errors that lead to unpredictable response of digital systems. Besides classical topics, such as hazards and races, the analysis of malfunctions in real circuits is also included. After defining the notion of behavior and nondeterministic response, a general approach for detecting such design problems through algebraic analysis is presented. Compared with existing simulation methods, the algebraic technique provides results of improved accuracy. Another basic advantage is the ability to accomodate modular synthesis of digital systems. Examples show how the proposed methods deal with sequential circuits under various delay assumptions. In particular, analysis of designs based on nominal delay parameters and on window delays is presented. A novel method, aiming at spike detection, is also presented. The ability of the algebraic analysis to detect errors in a modular design environment is illustrated by means of an example. Finally, the topic of nondeterministic behavior at RTL is briefly discussed. Notably, an algebraic method for deriving setup and hold time constraints from the circuit delay parameters is proposed.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127406691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
System Facilities for CAD Databases CAD数据库的系统设施
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804511
C. Eastman
{"title":"System Facilities for CAD Databases","authors":"C. Eastman","doi":"10.1145/800139.804511","DOIUrl":"https://doi.org/10.1145/800139.804511","url":null,"abstract":"In this paper, an attempt is made to lay out the special needs of design databases, as compared to the facilities provided in conventional database systems now commercially available. The paper starts from a point of commonality and focusses on the limitations and shortcomings commonly found in current database systems. It is impossible and unwise to make universal statements about DBMS capabilities. Instead, the goal is to identify those special features that, by their capability, provide distinctions beyond the general notions of speed and ratio of logical size to physical size.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127066623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
An Automatic Routing System for High Density Multilayer Printed Wiring Boards 高密度多层印刷线路板的自动布线系统
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804580
I. Nishioka, Takuji Kurimoto, Hisao Nishida, Seiji Yamamoto, T. Chiba, T. Nagakawa, T. Fujioka, M. Uchino
{"title":"An Automatic Routing System for High Density Multilayer Printed Wiring Boards","authors":"I. Nishioka, Takuji Kurimoto, Hisao Nishida, Seiji Yamamoto, T. Chiba, T. Nagakawa, T. Fujioka, M. Uchino","doi":"10.1145/800139.804580","DOIUrl":"https://doi.org/10.1145/800139.804580","url":null,"abstract":"Recent advances in the packaging technology of microelectronics have changed the design rules for printed wiring boards (PWB's) such that the number of wiring tracks between adjacent pins of an ordinary dual in line package (DIP) is allowed to be two or more, and the number of signal layers to be laminated is often required to be four or more. When the packaging density or scale of a PWB augments to such an extent, conventional routing schemes are confronted with various difficulties. The present paper describes a new routing system which can cope with such high density PWB's, for which the maximum numbers of layers to be laminated, circuit modules to be mounted, and signal nets are admitted up to 16, 2,000 and 4,000, respectively. The system described operates on a PDP 11/34 computer coupled with a TEKTRONIX 4014 graphics terminal. A set of implementation results are also shown to reveal how much the described system contributes to the reduction of time and labor incurred in laying out multilayer PWB's of high density.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126488747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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