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An Optimized ATPG 优化的ATPG
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804559
S. Mourad
{"title":"An Optimized ATPG","authors":"S. Mourad","doi":"10.1145/800139.804559","DOIUrl":"https://doi.org/10.1145/800139.804559","url":null,"abstract":"This paper describes a hierarchical approach to the detection of the critical faults of a digital board, i.e., those most likely to occur. The failure probabilities of the nodes of a board are estimated and used as weights in selecting the nodes for fault detection. The study has indicated both a saving in pattern generation and a higher fault detection per pattern. This approach introduces a new definition of fault coverage. The approach is also applicable to analog circuits. In addition, it allows for continual incorporation of field data, thus improving the estimation of the failure probabilities.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128372632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Data Structure for Interactive Placement of Rectangular Objects 矩形对象交互式放置的数据结构
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804533
V. Jayakumar
{"title":"A Data Structure for Interactive Placement of Rectangular Objects","authors":"V. Jayakumar","doi":"10.1145/800139.804533","DOIUrl":"https://doi.org/10.1145/800139.804533","url":null,"abstract":"A data structure suitable for interactive placement of disjoint rectangular objects is presented. Area available for placing new objects is described in terms of a unique set of maximum empty rectangles (MERs), each of these MERs bounded by objects already placed or by the boundary. Algorithms for addition and deletion of objects have been developed. Deletion is achieved by using the addition procedure itself. Information can readily be derived from the data structure to identify regions where a given object may be placed, to determine whether a new object can be placed if an existing one is removed, to assess restrictions on linear dimensions and areas of objects that can be placed etc. Though the scheme has been developed for automated layout of PCBs and ICs, it is applicable to other areas such as layout and modification of shopping centers and cities, utilization of warehouse space etc. A distinct feature of the method is that the extent of search to update the data structure need not increase with the number of objects placed or with the density of placement.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115009986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An Integrated Mask Artwork Analysis System 一种集成的面具图像分析系统
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804540
T. Mitsuhashi, Toshiaki Chiba, M. Takashima, Kenji Yoshida
{"title":"An Integrated Mask Artwork Analysis System","authors":"T. Mitsuhashi, Toshiaki Chiba, M. Takashima, Kenji Yoshida","doi":"10.1145/800139.804540","DOIUrl":"https://doi.org/10.1145/800139.804540","url":null,"abstract":"A new LSI artwork analysis and processing system, called EMAP, is described with algorithms, a database schema and applications. EMAP provides the designer with the artwork verification and processing tools which include mask artwork processing, geometrical design rule checking, connectivity analysis and electrical circuit parameter calculation. The circuit connectivity data derived from the mask artwork data is used for input to a logic simulator, a timing simulator, a circuit simulator and a circuit schematic generator.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133195149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
The Management of Engineering Changes Using the Primus System 运用Primus系统管理工程变更
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804555
Felix P. Mallmann
{"title":"The Management of Engineering Changes Using the Primus System","authors":"Felix P. Mallmann","doi":"10.1145/800139.804555","DOIUrl":"https://doi.org/10.1145/800139.804555","url":null,"abstract":"During the development of electronic products, engineering changes cannot normally be avoided. An effective method of handling EC's using the PRIMUS system is described. The basic features are a central database used in interactive mode and the possibility of storing all states of a design at the same time. The increase of data is by about 10%, but the savings in computer time are more than 50% in the design correction loops.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132468010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The Incorporation of Functional Level Element Routines into an Existing Digital Simulation System 将功能级元素例程集成到现有数字仿真系统中
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804561
E. Thompson, Patrick G. Karger, W. R. Read, D. Ross, John Smith, Richard von Blucher
{"title":"The Incorporation of Functional Level Element Routines into an Existing Digital Simulation System","authors":"E. Thompson, Patrick G. Karger, W. R. Read, D. Ross, John Smith, Richard von Blucher","doi":"10.1145/800139.804561","DOIUrl":"https://doi.org/10.1145/800139.804561","url":null,"abstract":"CC-TEGAS3 is a digital logic simulation system containing subsystems which can perform three different modes of simulation. These modes are used for logic or design verification, worst case timing analysis, and fault simulation. The basic device models are for Boolean gates, a wide range of flip-flops and latches, and a number of MOS elements such as transfer gates. A comprehensive list of functional level device models were incorporated into the system and the resulting system is called CC-TEGAS4. This approach was considered advantageous for today's technology, and an absolute necessity for the LSI and VLSI technologies that are forthcoming. This paper is concerned with the problems encountered and some of the techniques used to implement these functional level models, and results obtained in terms of reduction in required computer resources needed to simulate a network utilizing these new models.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133400953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Issues in IC Implementation of High Level, Abstract Designs 高级抽象设计集成电路实现中的问题
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804516
Jin H. Kim, D. Siewiorek
{"title":"Issues in IC Implementation of High Level, Abstract Designs","authors":"Jin H. Kim, D. Siewiorek","doi":"10.1145/800139.804516","DOIUrl":"https://doi.org/10.1145/800139.804516","url":null,"abstract":"With the exponential explosion in chip complexity there is a growing need for high level design aids. A preliminary experiment was conducted in mating a hierarchical, top-down DA system for data paths with an existing IC placement and router. Nine designs ranging in complexity from 7 to 150 register transfers were synthesized. Strong correlations were observed between high level, abstract measures and final placed and routed chip area. It was observed that use of logic primitives of a moderate level abstraction yielded a 50% savings in placed and routed chip area.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121774112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An Implementation of a Saturated Zone Multi-Layer Printed Circuit Board Router 饱和区多层印刷电路板路由器的实现
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804536
M. Lorenzetti, Robert J. Smith
{"title":"An Implementation of a Saturated Zone Multi-Layer Printed Circuit Board Router","authors":"M. Lorenzetti, Robert J. Smith","doi":"10.1145/800139.804536","DOIUrl":"https://doi.org/10.1145/800139.804536","url":null,"abstract":"A new multi-layer printed circuit board routing technique is presented which combines two existing algorithms with a new cost function. The present implementation of this new technique handles up to four layers at a time. The earlier works are overviewed and enhancements incorporated in the new implementation are pointed out. Experimental results obtained using this new router on printed circuit boards of various sizes and routing densities are also described.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125990198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The Interchange Algorithms for Circuit Placement Problems 电路布置问题的交换算法
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804581
L. C. Cote, Arvind M. Patel
{"title":"The Interchange Algorithms for Circuit Placement Problems","authors":"L. C. Cote, Arvind M. Patel","doi":"10.1145/800139.804581","DOIUrl":"https://doi.org/10.1145/800139.804581","url":null,"abstract":"This paper discusses the applications of interchange procedures to solve circuit placement problems. A theoretical analysis to guage the quality of solutions is presented. Two interchange algorithms (Algo I and Algo II) are programmed and tested for moderate size placement problems. Algo II is an improved version of Algo I. On the basis of the limited computational results. Algo II seems to provide significant improvements without increased computation cost.\u0000 The interchange procedure is widely utilized to find approximate solutions for combinatorial problems such as traveling salesman, facility locations, module placements, etc. There are many variations of the interchange procedure. However, the variations are generally limited to the procedure of selecting elements for possible exchanges. The different combinations (solutions) are systematically generated by interchanging only a few elements at a time. A combination which does not improve the value of some norm is rejected. A combination which improves the value of this norm is accepted and one tries to find another combination for further improvement. This is continued until one cannot improve the value of the norm. The search is terminated in a finite number of steps. Computational considerations limit the testing to only pairwise exchanges of elements. Thus, only a small subset of all the possible combinations are generated, and this generally results in suboptimum or local solutions. Even suboptimum solutions of very large problems (more than 100 nodes) can be computationally very expensive. Interchange procedures (as shown in Section 4) compete quite well with other heuristic techniques in regard to both computational time and quality of solutions.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125541519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Practical Automated Design of LSI for Large Computers 大型计算机用LSI的实用自动化设计
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804585
J. Singleton, N. R. Crocker
{"title":"Practical Automated Design of LSI for Large Computers","authors":"J. Singleton, N. R. Crocker","doi":"10.1145/800139.804585","DOIUrl":"https://doi.org/10.1145/800139.804585","url":null,"abstract":"The design of large computers using LSI techniques requires relatively large numbers of different designs in relatively small quantities. The paper describes a system of designing integrated circuits rapidly and reliably in this environment using the Uncommitted Logic Array (Master Slice) approach. An integrated design, validation and production system has been developed from logical input to pattern generator tape production which takes away the need for knowledge of Silicon Layout techniques from the integrated circuit designer","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124561952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development in Verification of Design Correctness 设计正确性验证的发展
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804525
W. E. Cory, W. M. V. Cleemput
{"title":"Development in Verification of Design Correctness","authors":"W. E. Cory, W. M. V. Cleemput","doi":"10.1145/800139.804525","DOIUrl":"https://doi.org/10.1145/800139.804525","url":null,"abstract":"This paper reviews recent developments in the verification of digital systems designs. The emphasis is on proof of functional correctness. Some of the techniques reviewed are symbolic simulation (including parallel simulation of HDL descriptions), dataflow verfication by grammar construction, comparison of manually generated design with automated design, and functional abstraction.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115124670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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