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SLIM--The Translation of Symbolic Layouts into Mask Data SLIM——符号布局到掩码数据的转换
17th Design Automation Conference Pub Date : 1988-06-01 DOI: 10.1145/62882.62906
A. Dunlop
{"title":"SLIM--The Translation of Symbolic Layouts into Mask Data","authors":"A. Dunlop","doi":"10.1145/62882.62906","DOIUrl":"https://doi.org/10.1145/62882.62906","url":null,"abstract":"A new form of symbolic layout for integrated circuits is coupled with a mask compaction procedure which removes excess space while guaranteeing that all design rules are met. Trade-offs between X and Y compaction are made based on critical path information. Two types of compaction are used to minimize mask area and computer run-time. Additional procedures reduce mask area by inserting jogs at strategic locations in the layout. A partitioned data base is used to store mask data in a hierarchical manner. The symbolic layout and mask compaction procedures require only 30 to 50 percent of the time traditionally needed to do equivalent hand layouts. The global guidance information is used to control local compaction (clustering), automatic jog insertion, and global compaction procedures. These procedures make extensive use of design rule tolerance tests in reducing the area of the \"initial placement\" mask layout. The symbolic input is a loose topological description of the layout made up of single-connection-per-side symbols (e.g., transistors, interlayer contacts, etc.) and multiple-connection-per-side symbols (e.g., predefined RAMs, ROMs, flip-flops, etc.). The output is a legal mask description and graphical displays.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130085748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
SCOAP: Sandia Controllability/Observability Analysis Program SCOAP:桑迪亚可控性/可观察性分析程序
17th Design Automation Conference Pub Date : 1988-06-01 DOI: 10.1145/62882.62929
Lawrence H. Goldstein, E. L. Thigpen
{"title":"SCOAP: Sandia Controllability/Observability Analysis Program","authors":"Lawrence H. Goldstein, E. L. Thigpen","doi":"10.1145/62882.62929","DOIUrl":"https://doi.org/10.1145/62882.62929","url":null,"abstract":"SCOAP is a program developed at Sandia National Laboratories for the analysis of digital circuit testability. Testability is related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively. This paper reviews the testability analysis algorithms and describes their implementation in the SCOAP program.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121046304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 146
Test Generation Costs Analysis and Projections 测试生成成本分析和预测
17th Design Automation Conference Pub Date : 1988-06-01 DOI: 10.1145/62882.62927
P. Goel
{"title":"Test Generation Costs Analysis and Projections","authors":"P. Goel","doi":"10.1145/62882.62927","DOIUrl":"https://doi.org/10.1145/62882.62927","url":null,"abstract":"Empirical observations are used to derive analytic formulae for test volumes, parallel fault simulation costs, deductive fault simulation costs, and minimum test pattern generation costs for LSSD logic structures. The formulae are significant in projecting growth trends for test volumes and various test generation costs with increasing gate count G. Empirical data is presented to support the thesis that test volume grows linearly with G for LSSD structures that cannot be partitioned into disjoint substructures. Such LSSD structures are referred to as \"coupled\" structures. Based on empirical observation that the number of latches in an LSSD logic structure is proportional to the gate count G, it is shown that the logic test time for coupled structures grows as G/sup 2/. It is also shown that (i) parallel fault simulation costs grow as G/sup 3/ (ii) deductive fault simulation costs grow as G/sup 2/, and (iii) the minimum test pattern generation costs grow as G/sup 2/. Based on these projections some future testing problems become apparent.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131755677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
Interactive Wiring System 交互式布线系统
17th Design Automation Conference Pub Date : 1981-04-01 DOI: 10.1109/MCG.1981.1673871
F. D. Skinner
{"title":"Interactive Wiring System","authors":"F. D. Skinner","doi":"10.1109/MCG.1981.1673871","DOIUrl":"https://doi.org/10.1109/MCG.1981.1673871","url":null,"abstract":"The Interactive Wiring System (IWS) is a highly interactive graphic application originally developed for the embedding of overflow wires on cards, boards and other high-level packages. It has since been expanded to support component placement, I/O assignment and service net manipulation. The programs were developed for IBM's internal use and are not marketed by IBM. An overview of how IWS interfaces with the IBM Design Automation System (EDS - Engineering Design System) is followed by a brief description of the IWS model. Representative functions are described as seen by the IWS user. Examples of how IWS has impacted the design process at various IBM locations are included. A separate section briefly addresses the display technology implications of some of the graphical display techniques used by IWS. The paper concludes with a brief description of changes being considered to enhance the flexibility of the IWS model for high-level packages and to allow support of chip-level packages.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122373441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Complexity Theory and Design Automation 复杂性理论与设计自动化
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804563
W. Donath
{"title":"Complexity Theory and Design Automation","authors":"W. Donath","doi":"10.1145/800139.804563","DOIUrl":"https://doi.org/10.1145/800139.804563","url":null,"abstract":"Complexity Theory is discussed and its relationship to Physical Design (i.e. Placement/Wiring) and Test Pattern Generation is shown and developed.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114670794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 80
A Line-Expansion Algorithm for the General Routing Problem with a Guaranteed Solution 一般路由问题的一种有保证解的线路展开算法
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804534
W. Heyns, W. Sansen, H. Beke
{"title":"A Line-Expansion Algorithm for the General Routing Problem with a Guaranteed Solution","authors":"W. Heyns, W. Sansen, H. Beke","doi":"10.1145/800139.804534","DOIUrl":"https://doi.org/10.1145/800139.804534","url":null,"abstract":"A new routing algorithm is presented which is based on the expansion of a line in the direction perpendicular to the line. The line-expansion principle is first applied to the single layer routing problem. For the routing on two layers only some minor modifications have to be made. An important extension is added in which the search for an interconnection from a given point is initiated in more than one direction at the same time. The major advantage of the line-expansion algorithm over the well-known line-search algorithm is the guarantee that always a solution will be found if one exists.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116866213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
Digital Test Generation and Design for Testability 数字测试生成与可测试性设计
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804527
J. Grason, Andrew W. Nagle
{"title":"Digital Test Generation and Design for Testability","authors":"J. Grason, Andrew W. Nagle","doi":"10.1145/800139.804527","DOIUrl":"https://doi.org/10.1145/800139.804527","url":null,"abstract":"This paper is a tutorial intended primarily for individuals just getting started in digital testing. Basic concepts of testing are described, and the steps in the test development process are discussed. A pragmatic approach to test sequence generation is presented, oriented towards ICs interconnected on a board. Finally, design for testability techniques are described, with an emphasis on solving problems that appeared during the test generation discussion.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116558568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A Prototyping and Simulation Approach to Interactive Computer System Design 交互式计算机系统设计的原型与仿真方法
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804588
Paul R. Hanau, David R. Lenorovitz
{"title":"A Prototyping and Simulation Approach to Interactive Computer System Design","authors":"Paul R. Hanau, David R. Lenorovitz","doi":"10.1145/800139.804588","DOIUrl":"https://doi.org/10.1145/800139.804588","url":null,"abstract":"The design and development of user interfaces to interactive computer systems has suffered from the inability of designers to easily express their design concepts in concrete, comprehensive, and comprehensible working models. An effort is underway to improve the process of man-machine dialogue design and implementation by developing prototyping and simulation tools to be used as an integral part of the specification and design process. These include an interactive display building utility and a syntax-driven interactive dialogue controller.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130334042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Fast Maze Router with Iterative Use of Variable Search Space Restriction 一种基于可变搜索空间约束迭代的快速迷宫路由器
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804535
F. Tada, Kiyoshi Yoshimura, Takashi Kagata, T. Shirakawa
{"title":"A Fast Maze Router with Iterative Use of Variable Search Space Restriction","authors":"F. Tada, Kiyoshi Yoshimura, Takashi Kagata, T. Shirakawa","doi":"10.1145/800139.804535","DOIUrl":"https://doi.org/10.1145/800139.804535","url":null,"abstract":"This paper describes a new method of restricting search space for maze routing, to achieve a higher routing completion ratio and shorter machine time. The router is applied iteratively, expanding the width of L-shaped search space restriction from narrow one to wider ones successively. Using this method, machine time was reduced to one-fourth and the routing completion ratio was more than 10% higher in experimental comparison with singly restricted routers of no iteration. This paper also discusses an analysis to help to decide the iteration number and L-shaped path width.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115941842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
The Standard Transistor Array (STAR) Part II Automatic Cell Placement Techniques 标准晶体管阵列(STAR)第二部分自动单元放置技术
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804569
G. W. Cox, B. Carroll
{"title":"The Standard Transistor Array (STAR) Part II Automatic Cell Placement Techniques","authors":"G. W. Cox, B. Carroll","doi":"10.1145/800139.804569","DOIUrl":"https://doi.org/10.1145/800139.804569","url":null,"abstract":"Layout of a STAR device consists of the placement of standard cells (circuit elements) on the array and the routing of conductors between cells. Cell placement must be such that routing is not hindered. Also, placement procedures must be cost effective and easy to implement on a digital computer. A placement procedure for STARs is described in this paper that satisfies these characteristics. The procedure attempts to optimize the placement with respect to several criteria including expected routing channel usage and routing VIA requirements. Computer implementations of the procedure are discussed. Experimental results are presented which indicate that the procedure yields near-optimum results in computationally convenient amounts of time.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134437362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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