{"title":"The Standard Transistor Array (STAR) Part I-A Two-Layer Metal Semicustom Design System","authors":"J. Gould, T. M. Edge","doi":"10.1145/800139.804519","DOIUrl":"https://doi.org/10.1145/800139.804519","url":null,"abstract":"The Standard Transistor Array (STAR) design system is a two-layer metal semicustom approach to generating random logic MOS digital circuits. The STAR design system is a part of the Large Scale Microelectronics Computer-Aided Design and Test (CADAT) system [1]. The STAR design automated system includes a STAR-PLACE automatic placement program, a STAR-COMPILE compiling program, a STAR-ROUTE automatic routing program, a STAR-PRINT display program, and the ARTWORK-MANART artwork generation program. The basic STAR array, array technologies, STAR logic cell design, STAR application software, and example STAR circuit layouts are discussed in this paper.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"65 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132432757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ALEX: A Conversational, Hierarchical Logic Design System","authors":"K. A. Duke, K. Maling","doi":"10.1145/800139.804545","DOIUrl":"https://doi.org/10.1145/800139.804545","url":null,"abstract":"A fresh look at the technical problems of present-day logic design and at the principal activities of the logic designer resulted in a system for hierarchical logic design. It is supported by a novel, high-level graphic language to describe the connections between logical devices. A major concern was to ensure that processes invoked by a user while designing, modifying and testing logic normally require only a few seconds or, on rare occasions, a few minutes to execute.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129667049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. L. Smith, Sharon A. Stephens, L. Tripp, Wayne L. Warren
{"title":"A Tool to Support Design Automation in Batch Manufacturing","authors":"G. L. Smith, Sharon A. Stephens, L. Tripp, Wayne L. Warren","doi":"10.1145/800139.804557","DOIUrl":"https://doi.org/10.1145/800139.804557","url":null,"abstract":"The development of integrated computer-aided manufacturing systems demands that the generic functions and common information be identified and classified. This paper presents an automated approach for modeling the functional aspect of an integrated manufacturing system. The approach is called IDEF/sub 0/ and is being used by the Air Force ICAM program for all system development. The rationale, design approach and implementation of the automated tool AUTOIDEF/sub 0/, which supports the use of IDEF/sub 0/, is presented.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126318074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automation of Design for Uncommitted Logic Array","authors":"F. Ramsay","doi":"10.1145/800139.804518","DOIUrl":"https://doi.org/10.1145/800139.804518","url":null,"abstract":"This paper explains the design automation strategy developed at the Ferranti Electronics C.A.D. Centre for the Uncommitted Logic Array (U.L.A.). This strategy was to develop a modular automated design system for the single layer metallisation U.L.A.'s which automatically referred a central design document - the logic diagram. The system handles the function of auto layout and checking. It also links into the logic analysis and test schedule verification system.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115621539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Computer-Aided Assignment of Manufacturing Tolerances","authors":"Arvind M. Patel","doi":"10.1145/800139.804521","DOIUrl":"https://doi.org/10.1145/800139.804521","url":null,"abstract":"This paper discusses the problem of assigning manufacturing tolerances in the development of a tolerance chart. A quantitative model is constructed so as to consider both the tolerance capability of the various processes used in the manufacture of a part, as well as the most effective way to combine tolerances in order to establish an overall tolerance. The variations of this model are discussed along with the manual trial and error method. It appears that significant reductions in manufacturing costs can be achieved by applying the automation methods presented in this paper.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124950806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Generalized Channel Router","authors":"Dave Hightower, R. Boyd","doi":"10.1145/800139.804507","DOIUrl":"https://doi.org/10.1145/800139.804507","url":null,"abstract":"A \"generalized\" channel router operates on horizontal and vertical channels generated from an irregular cell structure, and is free of a routing grid. Such a router can solve virtually any routing problem. It has two major phases: the global routing phase and the channel routing phase. This paper describes both phases as they have been implemented at TI. It concludes with a demonstration of the versatility of the router (it is used to solve the Hampton Court Maze) and with applications of the router in TI's I2L (Integrated Injector Logic) / STL (Schottky Transistor Logic) Automatic Layout System.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130393835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Ulrich, D. Lacy, N. Phillips, J. Tellier, M. Kearney, T. Elkind, R. Beaven
{"title":"High-Speed Concurrent Fault Simulation with Vectors and Scalars","authors":"E. Ulrich, D. Lacy, N. Phillips, J. Tellier, M. Kearney, T. Elkind, R. Beaven","doi":"10.1145/800139.804558","DOIUrl":"https://doi.org/10.1145/800139.804558","url":null,"abstract":"Basic goals for logic and fault simulation are accuracy, execution speed, and modeling ease. Accuracy means that adequate state and timing detail must be maintained, and that good and faulted networks must be simulated with equal accuracy. High speed simulation is desirable to perform massive fault simulations of large networks, and modeling ease is desirable to build models easily and quickly.\u0000 It should be observed that some of the above goals are in mutual conflict. For example, modeling ease and high execution speed are normally only achievable by a sacrifice in accuracy, and high accuracy is only possible by more elaborate modeling efforts or slower execution speeds, or both. As a consequence it becomes important to achieve a balance between these goals. The balance achieved here, in part dictated by the demands of fault simulation, emphasizes execution speed, adequate accuracy, and a simple modeling method.\u0000 A new logic and fault simulator, VOTE (Verification of Test Effectiveness) is described. The specifics to be described here fall into two categories: those which are of general interest, and those which are strictly implementation items.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"277 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114348854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Design and Implementation of Fault Insertion Capabilities for ISPS","authors":"J. Northcutt","doi":"10.1145/800139.804529","DOIUrl":"https://doi.org/10.1145/800139.804529","url":null,"abstract":"Fault tolerance is an important attribute of most computer systems, and to be effective it must be an explicit objective from the beginning of the design process. Inserting faults into a simulation of the machine and observing its behavior is a thorough and economical technique for evaluating prospective fault detection, diagnosis, recovery, and repair mechanisms. As systems become larger due to rising semiconductor integration, the expense of these fault simulations increasingly necessitates that they be performed at higher levels of abstraction (such as the register transfer level) rather than lower (such as the gate level). This can achieve major cost savings without significantly compromising fault coverage. This paper describes the design and implementation of a high level fault insertion mechanism for the Instruction Set Processor Specification (ISPS) simulator. The ISPS simulator was chosen because it is an interactive, high level simulator which is capable, mature, and widely used and accepted. The faults which can be simulated include hard and transient, deterministic and probabilistic, stuck-at and bridged, data, control, and operation types. These facilities have been implemented and demonstrated to be sound in both concept and implementation. They have been incorporated as a standard feature in the latest release of the ISPS simulator.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123713590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Interactive Test Data System for LSI Production Testing","authors":"H. D. Schnurmann, R. M. Peters","doi":"10.1145/800139.804556","DOIUrl":"https://doi.org/10.1145/800139.804556","url":null,"abstract":"This paper describes a software system, ITDS, which supplies a chip or module tester with test data. There are two major components to the system: an interactive data entry system, ITLG; and a generator of environmental test data, SPEC/GEN. By \"conversing\" with its user, ITLG creates a technology library from a document of circuit specifications. The user does not need to be familiar with the tester. ITLG will guide the user by showing him how to enter the necessary data, by auditing his response and by informing him of the accuracy of his response. The SPEC/GEN system uses the technology library from ITLG to create a data set of final test values. These values are the result of calculations that consider the technology, tester, and the I/O electrical characteristics of the part number to be tested. This paper also shows how data set for final test is automatically created.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130129574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Weaknesses of Commercial Data Base Management Systems in Engineering Applications","authors":"Thomas Sidle","doi":"10.1145/800139.804512","DOIUrl":"https://doi.org/10.1145/800139.804512","url":null,"abstract":"In recent years many engineering organizations have come to the conclusion that a centralized data base, containing all of their design/manufacturing data, is the most cost effective solution to their needs. Increasing numbers of the designers of these central data bases are utilizing commercially available DBMS packages to implement their systems. There are many good reasons for using an \"off the shelf\" system, but the results often do not live up to the expectations. This paper attempts to explain why this is so, and to identify features which should be in an Engineering Data Base Management System, but which are not available in commercial DBMS packages at the present time.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128529500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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