{"title":"The Complexity of Design Automation Problems","authors":"S. Sahni, Atul Bhatt","doi":"10.1145/800139.804562","DOIUrl":"https://doi.org/10.1145/800139.804562","url":null,"abstract":"This paper reviews several problems that arise in the area of design automation. Most of these problems are shown to be NP-hard. Further, it is unlikely that any of these problems can be solved by fast approximation algorithms that guarantee solutions that are always within some fixed relative error of the optimal solution value. This points out the importance of heuristics and other tools to obtain algorithms that perform well on the problem instances of \"interest\".","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"289 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116239438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Gate Assignment and Pack Placement: Two Approaches Compared","authors":"Frank Luebbert, Mike Ulrey","doi":"10.1145/800139.804572","DOIUrl":"https://doi.org/10.1145/800139.804572","url":null,"abstract":"In this paper we discuss mathematical models for the gate assignment and pack placement problems. Relative to objective functions to be described, heuristic methods of solution are discussed, one for gate assignment and two for pack placement. Performance figures for two actual boards are presented, together with a comparison to manual layout for one of the boards.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122869568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Slide Simulator: A Facility for the Design and Analysis of Computer Interconnections","authors":"A. Altman, A. C. Parker","doi":"10.1145/800139.804524","DOIUrl":"https://doi.org/10.1145/800139.804524","url":null,"abstract":"Interconnection design can have a profound effect on the price and performance of a digital system. This paper describes a new simulation facility that is designed to allow the user to describe and simulate the behavior of an interconnected system. The simulator provides the capability to devise, debug, and evaluate digital interconnection schemes. The user first writes a description of the system interconnections using the hardware descriptive language SLIDE. The UNIBUS, for example, has been described in SLIDE. The description is then compiled into SIMULA code, and linked by the user with other SIMULA or SLIDE modules which probabilistically or deterministically modet the hardware that drives the interconnections. The simulation then proceeds under interactive user control.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130504369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cell Map Representation for Hierarchical Layout","authors":"J. Soukup, J. Royle","doi":"10.1145/800139.804591","DOIUrl":"https://doi.org/10.1145/800139.804591","url":null,"abstract":"In the hierarchical layout of rectangular blocks, the routing area naturally breaks into a set of adjacent rectangles. These rectangles can be used as a basis for both loose routing and the final track assignment. The paper explores some ways of structuring the required data. More details about generalized Lee routing, and practical results are left for verbal presentation.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126540635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A New Test Pattern Generation System","authors":"Yacoub M. El-Ziq","doi":"10.1145/800139.804513","DOIUrl":"https://doi.org/10.1145/800139.804513","url":null,"abstract":"This paper discusses the main shortcomings of existing software test pattern generation systems and describes the development of a new system. The new system will be developed in two phases. The first phase is called the scan-in/scan-out test generation sub-system. This sub-system will be used for testing designs which have 100% scan-in/scan-out (reading or writing of every register from external world is possible). The second phase will include the development of efficient general functional models. The test generation system to be developed in the first phase will be updated to incorporate the capability of handling such models. The functional models include general-combinational, register, counter ROM, RAM, and microprocessor. In this paper, only, an outline of some of the distinct features of the system will be described.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124672545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Verification of Timing Constraints on Large Digital Systems","authors":"T. McWilliams","doi":"10.1145/62882.62928","DOIUrl":"https://doi.org/10.1145/62882.62928","url":null,"abstract":"A new approach to the verification of the timing constraints on large digital systems has been developed. The associated algorithm is computationally very efficient, and provides early and continuous feedback about the timing aspects of synchronous sequential circuits as they are designed. It also provides means for conveniently verifying the design in sections, permitting the section-by-section timing verification of designs which are too large to examine as a unit on existing computer systems. A system using this algorithm has been implemented, and has been used to verify the timing constraints on the design of the S-1 Mark IIA processor.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128191252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Hierarchical Approach for Layout Versus Circuit Consistency Check","authors":"Shiu-Ping Chao, Yen-Son Huang, Lap Man Yam","doi":"10.1145/800139.804539","DOIUrl":"https://doi.org/10.1145/800139.804539","url":null,"abstract":"This paper describes a CAD program which checks the circuit topology and the electrical parameters from the IC layout data against the user supplied circuit descriptions. Taking advantage of the hierarchical characteristics of the layout data, the program achieves an efficient analysis and does a clear presentation of the results.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116519205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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