{"title":"Fault Diagnosis Based on Effect-Cause Analysis: An Introduction","authors":"M. Abramovici, M. Breuer","doi":"10.1145/800139.804514","DOIUrl":"https://doi.org/10.1145/800139.804514","url":null,"abstract":"This paper presents the basic concepts of a new fault diagnosis technique which has the following features: 1) is applicable to both single and multiple faults, 2) does not require fault enumeration, 3) can identify faults which prevent initialization, 4) can indicate the presence of nonstuck faults in the D.U.T., 5) can identify fault-free lines in the D.U.T. Our technique, referred to as effect-cause analysis, does not require a fault dictionary and it is not based on comparing the obtained response of the D.U.T. with the expected response, which is not assumed to be known. Effect-cause analysis directly processes the actual response of the D.U.T. to the applied test (the effect) to determine the possible fault situations (the causes) which can generate that response.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130791762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Shirakawa, N. Okuda, T. Harada, S. Tani, H. Ozaki
{"title":"Layout System for the Random Logic Portion of MOS LSI","authors":"I. Shirakawa, N. Okuda, T. Harada, S. Tani, H. Ozaki","doi":"10.1145/800139.804517","DOIUrl":"https://doi.org/10.1145/800139.804517","url":null,"abstract":"The random logic portion of an MOS LSI chip intended mainly for a calculator is constructed of an array of MOS complex gates, each composed of an MOS ratioless circuit with a multi-phase clocking system, and occupies ordinarily a considerable part of chip area. In this paper, a layout system for this portion of an LSI is described, which is constructed on the basis of a set of optimization heuristics. Experimental results of the layout system are also shown so as to reveal that the random logic portion can be realized in much the same area as can be done by manual layout.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126482366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Hierarchical Bit-Map Format for the Representation of IC Mask Data","authors":"James A. Wilmore","doi":"10.1145/800139.804590","DOIUrl":"https://doi.org/10.1145/800139.804590","url":null,"abstract":"An alternative representation to the usual outline description of geometric entities for IC mask artwork is described. Rather than identifying opaque areas of a mask by individual shape outlines as described by their corners' coordinates, both the opaque and transparent areas of the design are represented by 1's and 0's respectively in a grid pattern or \"bit map\" of the entire mask plane. A bit-map representation is well suited to many computer design aids which deal with IC layout data. Artwork output programs which require a \"MERGE\" operation on all shapes of each mask benefit from this data format since it already contains the merged version of each mask's geometric entities. The bit-map format especially promises to increase the operational efficiency of Boolean comparisons of various mask levels as performed by artwork analysis programs for locating design rule errors and for identifying circuit elements directly from the masks. A hierarchical scheme for describing the bit patterns of a mask efficiently is presented which limits the memory requirements of this data format to a size proportional to the usual outline description. Consequently the bit-map representation can be used not only in those computer aids where it supports program functions very well, but also as the central data format for a CAD system.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120955766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Multiple Delay Simulator for MOS LSI Circuits","authors":"H. Nham, A. Bose","doi":"10.1145/800139.804594","DOIUrl":"https://doi.org/10.1145/800139.804594","url":null,"abstract":"This paper describes a multiple delay simulator for MOS LSI circuits. The basic primitives for this simulator are MOS transistor structures where the transistors are evaluated logically. Integer rise and fall delays are associated with each transition and these delays are computed automatically based on device characteristics and circuit capacitances. The simulator has been extensively used for the design verification of production LSI chips.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114434081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Accurate Functional Level Concurrent Fault Simulator","authors":"M. d'Abreu, E. Thompson","doi":"10.1145/800139.804530","DOIUrl":"https://doi.org/10.1145/800139.804530","url":null,"abstract":"This paper describes the basic data structures and algorithms for a functional level fault simulator. The technique used is that of concurrent fault simulation. The algorithms and date structure support multi-signal value, gate and functional level device models. These algorithms and data structures also support the capability to simulate user defined faults and faults that cause timing violations. In the experimental version of the system, developed at the University of Texas, only classical stuck-at faults and faults that lead to timing discrepancies between the good and the faulty circuit were implemented. Minor additions to the data structures will allow the simulator to process non-classical faults like: (1) memory stuck-at, (2) user defined functional faults, (3) technology dependent shorted signal faults, etc. The accuracy achieved simulating a fault is consistent with the accuracy of the non-fault model.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117109595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An IC Design Station Needs a High Performance Color Graphic Display","authors":"N. Weste, B. Ackland","doi":"10.1145/800139.804541","DOIUrl":"https://doi.org/10.1145/800139.804541","url":null,"abstract":"Raster-scan color graphic displays provide increased visual feedback in many CAD areas. In addition the unique architecture of displays used for this purpose enable other CAD related problems to be solved within the hardware structure of the display. Achieving these features commensurate with human response times requires new architectures and algorithm development for color displays. This paper presents the architecture and some of the algorithms used in an advanced color display station for IC design. The display architecture is based on a high-speed microprogrammable bit-slice microprocessor which is optimised for the algorithms found in raster-scan graphics. A new algorithm for area filling is presented which is optimised for firmware implementation. The performance of the display in an I.C. design environment is described as an example of integration into a complete design station. A unique feature of the display system is the ability to pan, in real time, over a hierarchical data base.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126141049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design Integrity and Immunity Checking: A New Look at Layout Verification and Design Rule Checking","authors":"Edward J. McGrath, T. Whitney","doi":"10.1145/800139.804537","DOIUrl":"https://doi.org/10.1145/800139.804537","url":null,"abstract":"A program implementing a novel approach to layout verification is presented. The approach uses topological and device information to eliminate most false and unchecked errors. This technique, coupled with a hierarchical front end to eliminated redundant checks, is appropriate for layout verification of VLSI designs. Design rules appropriate for this technique, some usage rules in the context of structured design, and a discussion of the future of design rule checking are also presented.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121999869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Evolution of Design Automation to Meet the Challanges of VLSI","authors":"L. M. Rosenberg","doi":"10.1145/800139.804506","DOIUrl":"https://doi.org/10.1145/800139.804506","url":null,"abstract":"This paper presents the author's opinion of the major problems confronting Design Automation for VLSI and how Design Automation may evolve to meet these challenges. The paper first takes a historical look at the driving forces for Design Automation development by analyzing the evolution of Design Automation at RCA. It looks at both some successful and unsuccessful development efforts and attempts to isolate some of the criteria necessary for success. It review RCA's current LSI Design Automation capabilities and compares them to the challenge of VLSI. The major challenges -- layout, design verification and testability -- are discussed along with possible achievable solutions.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127741221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Efficient Placement and Routing Techniques for Master Slice LSI","authors":"H. Shiraishi, F. Hirose","doi":"10.1145/800139.804570","DOIUrl":"https://doi.org/10.1145/800139.804570","url":null,"abstract":"This paper deals with placement and routing techniques for master slice LSIs. The basic idea of both techniques is to make wiring density on the chip more uniform. Algorithms and some experimental results are described.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132753501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tohru Sasaki, A. Yamada, S. Kato, Terufumi Nakazawa, Kyoji Tomita, N. Nomizu
{"title":"MIXS: A Mixed Level Simulator for Large Digital System Logic Verification","authors":"Tohru Sasaki, A. Yamada, S. Kato, Terufumi Nakazawa, Kyoji Tomita, N. Nomizu","doi":"10.1145/800139.804596","DOIUrl":"https://doi.org/10.1145/800139.804596","url":null,"abstract":"A mixed level simulator, MIXS, is a logic verification tool which has multiple simulation capabilities. Main MIXS techniques are time wheel and selective trace algorithm for functional level simulation based on 'node' model concept and the linkage function of functional models, described in different detail, with network information. The mixed level simulation for large digital systems can be achieved very efficiently by using the above techniques.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130953699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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