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Design Process Analysis: A Measurement and Analysis Technique 设计过程分析:一种测量分析技术
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804564
Kenneth D. Yates
{"title":"Design Process Analysis: A Measurement and Analysis Technique","authors":"Kenneth D. Yates","doi":"10.1145/800139.804564","DOIUrl":"https://doi.org/10.1145/800139.804564","url":null,"abstract":"The range of services provided by design automation computing centers covers a broad spectrum. At one end of this spectrum is the center which provides pure computation power only. It is the user's responsibility to select, install, and tune the applications as well as to debug the resultant output. At the other end, it is the turnkey center which provides a near total service, relegating the user to job selection from a fixed set of installed applications with which to accomplish the design task.\u0000 The most effective design automation center combines the healthy attributes of these two extremes: buffering the user from I/S considerations, freeing him to concentrate on the design task; and providing the I/S center with application understanding and involvement to allow for proper system tuning.\u0000 The management information technique to achieve the desired objectives of improved user productivity and cycle time is referred to as design process analysis (DPA).\u0000 Detailed definitions of the data flow nodes as well as samples of the type of output obtainable from such a DPA system are covered in the presentation.\u0000 Management of an effective design automation center is a demanding and ongoing task, combining the skill levels of people, the capabilities of the DA applications, and the processing power of the computer center. Tuning this combination in a disciplined and orderly manner to provide the most timely and cost effective solutions to design problems requires an automatic data collection system driving a dynamic model of the design process. Utilizing the techniques of design process analysis, such an objective can be met","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115794827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SIDS - A Symbolic Interactive Design System 一个符号交互设计系统
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804542
D. Clary, R. Kirk, S. Sapiro
{"title":"SIDS - A Symbolic Interactive Design System","authors":"D. Clary, R. Kirk, S. Sapiro","doi":"10.1145/800139.804542","DOIUrl":"https://doi.org/10.1145/800139.804542","url":null,"abstract":"A new production approach to IC mask layout/checking is described which makes use of a combination of symbolic layout, computer checking and color graphics to resolve some of the problems in currently available layout systems. Techniques such as on-line design rule and connectivity checking, not found in other production systems, give the user \"instant\" feedback as he is designing.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132102060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Survey of Space Allocation Algorithms in Use in Architectural Design in the Past Twenty Years 近二十年建筑设计中的空间分配算法综述
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804526
R. Frew
{"title":"A Survey of Space Allocation Algorithms in Use in Architectural Design in the Past Twenty Years","authors":"R. Frew","doi":"10.1145/800139.804526","DOIUrl":"https://doi.org/10.1145/800139.804526","url":null,"abstract":"The paper presents methods of space allocation applicable to architectural design. These techniques have been developed in the past twenty years and are presented in this paper in such a way that they may also be applied to other desciplines. Four categories are presented that identify the variations in the dimensioning of the elements, either unit dimension or variable dimension, and the variation in the shape of the boundary, either a simple rectangle or a multi-faceted boundary.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123267351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Combinational Logic Synthesis from an HDL Description 从HDL描述的组合逻辑合成
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804584
S. Shiva
{"title":"Combinational Logic Synthesis from an HDL Description","authors":"S. Shiva","doi":"10.1145/800139.804584","DOIUrl":"https://doi.org/10.1145/800139.804584","url":null,"abstract":"Hardware Description Languages are used to input the details of a digital system into an automatic design system. An algorithm to synthesize combinational logic from the description in one such language (DDL) is discussed. A sample implementation and the cost comparison are provided.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123947144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Selecting and Successfully Implementing a Turnkey Computer Graphics System 选择并成功实现交钥匙计算机图形系统
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804589
F. Bliss, George M. Hyman
{"title":"Selecting and Successfully Implementing a Turnkey Computer Graphics System","authors":"F. Bliss, George M. Hyman","doi":"10.1145/800139.804589","DOIUrl":"https://doi.org/10.1145/800139.804589","url":null,"abstract":"Success with computer graphics depends upon the users as much as the system itself. This paper outlines procedures for selecting and successfully using an interactive computer graphics system. Ford Motor Company's experience with computer graphics is reviewed, followed by a brief description of the various types of graphics systems that are available. INITIAL PREPARATION examines the techniques used to evaluate graphic systems including formation of an evaluation team, and application analysis. GRAPHICS EVALUATION describes the methods used to test a graphics system, including benchmark specification and human engineering considerations. COMPUTER SYSTEM EVALUATION examines other factors in system selection: programming, communications, documentation, and service. SYSTEM START UP addresses site preparation, people preparation, system acceptance, and operator selection. Finally, operator TRAINING and SYSTEM MANAGEMENT are discussed.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117164536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Table Lookup Techniques for Fast and Flexible Digital Logic Simulation 快速灵活数字逻辑仿真的表查找技术
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804586
E. Ulrich
{"title":"Table Lookup Techniques for Fast and Flexible Digital Logic Simulation","authors":"E. Ulrich","doi":"10.1145/800139.804586","DOIUrl":"https://doi.org/10.1145/800139.804586","url":null,"abstract":"A well-known fundamental computer technique consists of the \"interpretation\" of naturally available or artifically formed, data items as addresses to perform table-lookups. Although well-known, this technique is still not exploited to its fullest potential. The power and extent of this technique as applied to logic simulation is demonstrated.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128446177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Functional Level Simulation at Raytheon 雷声公司的功能级仿真
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804597
Dan C. Nash, K. Russell, Paul Silverman, M. Thiel
{"title":"Functional Level Simulation at Raytheon","authors":"Dan C. Nash, K. Russell, Paul Silverman, M. Thiel","doi":"10.1145/800139.804597","DOIUrl":"https://doi.org/10.1145/800139.804597","url":null,"abstract":"Raytheon has enhanced its gate level simulation system (GRASS) to include a functional level simulation capability. This paper describes the features of the Functional Description Language (FDL), implementation features, recent results, and future plans for the system.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127193356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automation of Sheet Metal Design and Manufacturing 钣金设计与制造自动化
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804522
David W. Currier
{"title":"Automation of Sheet Metal Design and Manufacturing","authors":"David W. Currier","doi":"10.1145/800139.804522","DOIUrl":"https://doi.org/10.1145/800139.804522","url":null,"abstract":"This paper discusses operating procedures and programming for the automation of design and manufacturing of formed sheet metal parts. It's primary purpose is to examine the design procedure, programming and N/C data preparation used on an existing 3-D graphics system. The process relies on the accuracy, reliability, and speed of CAD/CAM.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132128411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A Mixed-Mode Simulator 混合模式模拟器
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804595
V. Agrawal, A. Bose, P. Kozak, H. Nham, E. Pacas-Skewes
{"title":"A Mixed-Mode Simulator","authors":"V. Agrawal, A. Bose, P. Kozak, H. Nham, E. Pacas-Skewes","doi":"10.1145/800139.804595","DOIUrl":"https://doi.org/10.1145/800139.804595","url":null,"abstract":"To provide flexibility and efficiency in logic and timing verification of MOS VLSI circuits, it is desirable that various portions of a circuit can be described and simulated at appropriate levels of detail. Such a capability is provided by the Mixed-Mode Simulator described here. This simulator allows different elements of a circuit to be modeled and simulated at different levels of detail. The modeling levels are MOS transistor level, logic gate level and functional level. The simulation levels are timing, multiple delay and unit delay. The simulator is being used on production LSI chips and its performance is discussed.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134376729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Verifying Deep Logic Hierarchies with ALEX 用ALEX验证深层逻辑层次结构
17th Design Automation Conference Pub Date : 1980-06-23 DOI: 10.1145/800139.804546
G. Koppelman, K. Maling
{"title":"Verifying Deep Logic Hierarchies with ALEX","authors":"G. Koppelman, K. Maling","doi":"10.1145/800139.804546","DOIUrl":"https://doi.org/10.1145/800139.804546","url":null,"abstract":"A logic design whose structure has the form of a hierarchy is easily verified in a conversational environment. The verification process is based on an explicit methodology, supported by appropriate utilities. The paper describes the verification of the experimental Josephson signal processor control logic by means of the ALEX logic design system.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121371925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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