{"title":"over - cell路由器","authors":"D. Deutsch, P. Glick","doi":"10.1145/800139.804509","DOIUrl":null,"url":null,"abstract":"A program that produces single-layer planar routing over the cells for I2L and LST2L logic arrays is described. This router has been integrated into a layout system which was previously restricted to the layout of standard cell LSI chips. When used in conjunction with a channel router, the complete routing is produced automatically. This paper defines the over-the-cell routing problem, describes the algorithms for its solution, and presents typical routing results.","PeriodicalId":196513,"journal":{"name":"17th Design Automation Conference","volume":"201 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1980-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"42","resultStr":"{\"title\":\"An Over-The-Cell Router\",\"authors\":\"D. Deutsch, P. Glick\",\"doi\":\"10.1145/800139.804509\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A program that produces single-layer planar routing over the cells for I2L and LST2L logic arrays is described. This router has been integrated into a layout system which was previously restricted to the layout of standard cell LSI chips. When used in conjunction with a channel router, the complete routing is produced automatically. This paper defines the over-the-cell routing problem, describes the algorithms for its solution, and presents typical routing results.\",\"PeriodicalId\":196513,\"journal\":{\"name\":\"17th Design Automation Conference\",\"volume\":\"201 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1980-06-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"42\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"17th Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/800139.804509\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"17th Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/800139.804509","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A program that produces single-layer planar routing over the cells for I2L and LST2L logic arrays is described. This router has been integrated into a layout system which was previously restricted to the layout of standard cell LSI chips. When used in conjunction with a channel router, the complete routing is produced automatically. This paper defines the over-the-cell routing problem, describes the algorithms for its solution, and presents typical routing results.
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