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IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006最新文献

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A 17 dBm 64 GHz voltage controlled oscillator with power amplifier in a 0.13 /spl mu/m SiGe BiCMOS technology 一个17 dBm 64 GHz压控振荡器，功率放大器采用0.13 /spl mu/m SiGe BiCMOS技术
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651083
B. Welch, U. Pfeiffer
{"title":"A 17 dBm 64 GHz voltage controlled oscillator with power amplifier in a 0.13 /spl mu/m SiGe BiCMOS technology","authors":"B. Welch, U. Pfeiffer","doi":"10.1109/RFIC.2006.1651083","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651083","url":null,"abstract":"A 64 GHz voltage controlled oscillator with power amplifier is presented. It uses an LC type oscillator with a capacitively degenerated negative resistance core, and a class AB power amplifier to output 17 dBm of power with a phase noise of -100 dBc/Hz (at 600 kHz). The stand alone oscillator delivers 5 dBm of output power (8 dBm balanced) with phase noise of between -95 dBc/Hz and -100 dBc/Hz (at 600 KHz offset) and 2 GHz tuning range. Separate voltage rails of 4 V, 2 V, and 1 V are provided for the two stages of buffering and core, respectively, for a total power consumption of 130 mW. The PA is a class-AB push-pull amplifier made from two unbalanced cascode amplifiers with 15 dB power gain and 17 dBm saturated output power. The PA operates off the same 4 V rail as the VCO buffer, consuming up to 500 mW of power for power added efficiencies of between 6-10%","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"101 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116292193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Energy efficient OOK transceiver for wireless sensor networks 用于无线传感器网络的节能OOK收发器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651137
D. Daly, A. Chandrakasan
{"title":"Energy efficient OOK transceiver for wireless sensor networks","authors":"D. Daly, A. Chandrakasan","doi":"10.1109/RFIC.2006.1651137","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651137","url":null,"abstract":"A 1 Mbps 916.5 MHz OOK transceiver for wireless sensor networks has been designed in a 0.18-mum CMOS process. The RX has envelope detection based architecture with a highly scalable RF front end. The RX power consumption scales from 0.5 mW to 2.6 mW, with an associated sensitivity of -37 dBm to -65 dBm at a BER of 10-3. The TX consumes 3.8 mW to 9.1 mW with output power from -11.4 dBm to -2.2 dBm. The RX achieves a startup time of 2.5 mus, allowing for efficient duty cycling","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116315333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
High-performance crest factor reduction processor for W-CDMA and OFDM applications 用于W-CDMA和OFDM应用的高性能波峰因子降低处理器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651119
A. Wegener
{"title":"High-performance crest factor reduction processor for W-CDMA and OFDM applications","authors":"A. Wegener","doi":"10.1109/RFIC.2006.1651119","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651119","url":null,"abstract":"Highly linear wideband power amplifiers (PAs) are needed for code division multiple access (CDMA) and orthogonal frequency division multiplex (OFDM) modulations. Such PAs normally have low operating efficiency because of the high peak-to-average ratio (PAR) of CDMA and OFDM signals. By reducing the PAR of CDMA and OFDM signals, both PA acquisition and operating costs are decreased. We describe the GC1115 crest factor reduction processor, a 1.8M gate device fabricated in 130 nm CMOS process that operates at input and output sample rates up to 130 Msamp/sec. The GC1115 decreases the PAR of W-CDMA test model signals to 5.7 dB while meeting all signal quality requirements of 3GPP TS 25.141. The GC1115 achieves similar PAR improvement on OFDM signals","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122943153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Receiver RF front-end with 5GHz-band LC voltage-controlled oscillator and subharmonically-locked ring oscillator for 17GHz wireless applications 接收机射频前端采用5ghz频段LC压控振荡器和亚谐波锁环振荡器，适用于17GHz无线应用
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651179
A. Tasic, S.Y. Yue, D. Ma, W. Serdijn, J. Long, D. Harame
{"title":"Receiver RF front-end with 5GHz-band LC voltage-controlled oscillator and subharmonically-locked ring oscillator for 17GHz wireless applications","authors":"A. Tasic, S.Y. Yue, D. Ma, W. Serdijn, J. Long, D. Harame","doi":"10.1109/RFIC.2006.1651179","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651179","url":null,"abstract":"A 17GHz RF receiver front-end consisting of a low-noise amplifier, dual balanced mixers, an LC voltage-controlled oscillator, and a frequency tripler implemented using a ring oscillator is presented in this paper. The measured LC-VCO phase noise is -112dBc/Hz at 1MHz offset from a 5.7GHz carrier. For a 1.3-3V range in VCO tuning voltage, the locking range of the tripler is 5.5GHz (16.1GHz-21.6GHz). The receiver front-end conversion gain is 13.2dB with a noise figure of 7.1dB (SSB 50Omega) and a 3rd-order input intercept point of -6.2dBm. The 1.84mm 2 testchip draws 36mA from a 2.2V supply","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123591246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
31-34GHz low noise amplifier with on-chip microstrip lines and inter-stage matching in 90-nm baseline CMOS 基于片上微带线和级间匹配的31-34GHz低噪声放大器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651106
M. Sanduleanu, Gang Zhang, J. Long
{"title":"31-34GHz low noise amplifier with on-chip microstrip lines and inter-stage matching in 90-nm baseline CMOS","authors":"M. Sanduleanu, Gang Zhang, J. Long","doi":"10.1109/RFIC.2006.1651106","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651106","url":null,"abstract":"A Ka band low-noise amplifier in a 90-nm bulk CMOS technology is presented. A thin-film microstrip line with ground sidewalls is used for signal distribution, matching and load resonators. The low-noise amplifier comprises two identical cascode stages, with inter-stage matching as gain boosting. The gain boosting circuit improves the gain by 20% and the noise performance by 27% of the cascode LNA. The proposed amplifier achieves a peak power-gain of 19dB with a 3-dB bandwidth of 31 to 34GHz and a noise figure of 3dB in the middle of the band. No extra process options like MIM capacitors or thick oxide devices are used. The die size is 933 mum by 918 mum and the power consumption is 10mW from a 1.2V (plusmn10%) power supply","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124792000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
Minimization of via count in multiple-metal inductors performance characterization and physical modelling 多金属电感器性能表征和物理建模中通孔数的最小化
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651198
O. Murphy, K. McCarthy, P. Murphy
{"title":"Minimization of via count in multiple-metal inductors performance characterization and physical modelling","authors":"O. Murphy, K. McCarthy, P. Murphy","doi":"10.1109/RFIC.2006.1651198","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651198","url":null,"abstract":"High Q on-chip inductors are vital for modern RF ICs. A proven method of Q-enhancement is to use multiple metals stacked in a shunt manner, with a dense array of vias. The impact of fewer vias has not been investigated before. Here, we show that the same Q can be achieved with significantly fewer vias, thus simplifying the inductor layout. The traditional and new approaches are explained and physical models developed which give excellent agreement between simulations and measurements up to 6GHz","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124867202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Coupling effects of dual SiGe power amplifiers for 802.11n MIMO applications 802.11n MIMO应用中双SiGe功率放大器的耦合效应
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651092
Wei-Chun Hua, Po-Tsung Lin, Chun-Ping Lin, Che-Yung Lin, Huan-Lin Chang, Cheewee Liu, Tzu-Yi Yang, G. Ma
{"title":"Coupling effects of dual SiGe power amplifiers for 802.11n MIMO applications","authors":"Wei-Chun Hua, Po-Tsung Lin, Chun-Ping Lin, Che-Yung Lin, Huan-Lin Chang, Cheewee Liu, Tzu-Yi Yang, G. Ma","doi":"10.1109/RFIC.2006.1651092","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651092","url":null,"abstract":"The large-signal and small-signal coupling effects of dual SiGe power amplifiers (PAs) on a single chip for 802.11n multiple input multiple output (MIMO) applications are demonstrated for the first time. Deep trench isolation and grounded guard ring are used for crosstalk isolation at both transistor and circuit levels. The equivalent small-signal coupling at 2.45 GHz between two PAs is -30 dB. The PA delivers 18.1 dBm and 16.6 dBm with 3% EVM (OFDM, 64-QAM) in single and dual PA operation modes, respectively. The EVM degradation becomes severe as the relative interfering power level increases","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"15 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124629274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A fully-integrated +23-dBm CMOS triple cascode linear power amplifier with inner-parallel power control scheme 全集成+ 23dbm CMOS三级联码线性功率放大器，内并行功率控制方案
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651111
Hyoung-Seok Oh, C. Kim, Hyun-Kyu Yu, Choong-Ki Kim
{"title":"A fully-integrated +23-dBm CMOS triple cascode linear power amplifier with inner-parallel power control scheme","authors":"Hyoung-Seok Oh, C. Kim, Hyun-Kyu Yu, Choong-Ki Kim","doi":"10.1109/RFIC.2006.1651111","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651111","url":null,"abstract":"The low oxide breakdown voltage of CMOS power transistor and low power-added efficiency (PAE) at low power levels have been major challenging issues in the implementation of high-power linear power amplifiers (PAs), especially in deep sub-micron CMOS technology. In order to alleviate these problems, a triple cascode CMOS PA with inner-parallel power control scheme is presented. The proposed PA, fully-integrated in 0.18mum CMOS technology, delivers an output power of 23dBm with 35% PAE at 3.3V supply voltage. Since the thin-oxide transistors of the minimum feature size can be utilized as power transistors in the proposed PA, a high power gain of 19dB has been achieved even at single-stage. And PAE at an 8dB-backoff from the 1dB compression point (P1dB) of 20dBm has been measured as high as 12%","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125419703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Verification of RF SoCs: RF, analog, baseband and software 验证射频soc:射频，模拟，基带和软件
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651166
K. Muhammad, T. Murphy, R. Staszewski
{"title":"Verification of RF SoCs: RF, analog, baseband and software","authors":"K. Muhammad, T. Murphy, R. Staszewski","doi":"10.1109/RFIC.2006.1651166","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651166","url":null,"abstract":"Single-chip RF SoCs are seeing widespread acceptance in wireless applications. In this paper we address the issue of design verification of such complex ICs that accept input close to the RF carrier frequency and are analyzed for receiver BER performance and transmitter output distortion and phase noise by processing several thousand packets of baseband information while compensation algorithms are simultaneously executed. No comprehensive methodology exists to date for designing such complex systems. This paper present a novel approach that allows building complex RF SoC systems based on VHDL modeling and simulation and opens up major avenues of model development for RF and analog circuits. This approach has been successfully applied to verify two generations of digital RF processors in deep-submicron technologies","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130699235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A dual-band four-mode /spl Delta/-/spl Sigma/ frequency synthesizer 双频四模/spl Delta/-/spl Sigma/频率合成器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651125
Wei-Zen Chen, Dai-Yuan Yu
{"title":"A dual-band four-mode /spl Delta/-/spl Sigma/ frequency synthesizer","authors":"Wei-Zen Chen, Dai-Yuan Yu","doi":"10.1109/RFIC.2006.1651125","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651125","url":null,"abstract":"This paper describes the design of a dual-band, four-mode Delta-Sigma frequency synthesizer for WLAN a,b,g and Bluetooth applications. Integrating both a multi-modulus PLL and a 3rd order Delta-Sigma modulator in a single chip, the channel spacing of the RF synthesizer can be as low as 20 kHz and the frequency hopping time is less than 67 musec. A charge pump circuit is proposed to improve its linearity and the matching of the pumping currents. The measured phase noise at 1MHz offset are about -114 dBc/Hz and -116 dBc/Hz respectively at 5 GHz and 2.5 GHz frequency bands. Fabricated in a 0.18-mum CMOS process, the chip size is 1.95 mm2. The total power consumption is 19.54 mW from a 1.8 V power supply","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125474357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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