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IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006最新文献

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A low-noise 40-GS/s continuous-time bandpass /spl Delta//spl Sigma/ ADC centered at 2GHz 一个低噪声40-GS/s连续时间带通/spl Delta//spl Sigma/ ADC，中心为2GHz
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651147
T. Chalvatzis, S. Voinigescu
{"title":"A low-noise 40-GS/s continuous-time bandpass /spl Delta//spl Sigma/ ADC centered at 2GHz","authors":"T. Chalvatzis, S. Voinigescu","doi":"10.1109/RFIC.2006.1651147","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651147","url":null,"abstract":"A 2-GHz, continuous-time bandpass DeltaSigma analog-to-digital converter sampled with a 40-GHz clock was implemented in a 130-nm SiGe BiCMOS technology. It achieves an SNDR of 55 dB and 52 dB over 60 MHz and 120 MHz, respectively, and an SFDR of 61 dB with a single-ended IIP3 of +4 dBm. The center frequency is tunable from 1.8-2 GHz. It employs a Gm-LCVAR filter based on a MOS-HBT cascode transconductor with an NFmin of 2.3 dB. The ADC dissipates 1.6 W from a 2.5-V supply with a figure of merit of 18 pJ/sampled bit, including the contribution of the 40-GHz clock distribution network","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133566928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Tailoring on-chip inductors for low-noise ultra-wide-band receiver applications 为低噪声超宽带接收器应用定制片上电感器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651190
F. Chai, I. To, D. Hammock, M. Huang
{"title":"Tailoring on-chip inductors for low-noise ultra-wide-band receiver applications","authors":"F. Chai, I. To, D. Hammock, M. Huang","doi":"10.1109/RFIC.2006.1651190","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651190","url":null,"abstract":"Inductors have been proven to be an effective on-chip passive element in UWB receiver applications to simultaneously achieve noise and impedance matching. However, the conventional approach of optimizing on-chip inductor quality Q factor for low-GHz narrow-band applications is not appropriate for wideband UWB receiver front-end designs. This is especially severe for applications approaching 10GHz. Suitable inductor dimensions as well as the inductance values need to be carefully chosen to ensure an optimized noise performance and the manufacturability for consumer UWB radio products","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133875814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A WCDMA, GSM/GPRS/EDGE receiver front end without interstage SAW filter WCDMA, GSM/GPRS/EDGE接收器前端，无级间SAW滤波器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651078
Naveen K. Yanduru, Danielle Griffith, S. Bhagavatheeswaran, Chien-Chung Chen, Fikret Dulger, S. Fang, Y. Ho, K. Low
{"title":"A WCDMA, GSM/GPRS/EDGE receiver front end without interstage SAW filter","authors":"Naveen K. Yanduru, Danielle Griffith, S. Bhagavatheeswaran, Chien-Chung Chen, Fikret Dulger, S. Fang, Y. Ho, K. Low","doi":"10.1109/RFIC.2006.1651078","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651078","url":null,"abstract":"A dual mode RF receiver for DCS band in 90 nm CMOS is presented. The receiver uses direct conversion for WCDMA mode and uses 100 kHz low IF for GSM/GPRS/EDGE (GGE) mode. The receiver does not use an interstage SAW filter between LNA and mixer. The mixer stage is followed by a variable gain amplifier. Two times LO clock is provided from external source and a divide by two is used to generate quadrature clocks. The receiver has a NF of 2.9 dB and meets all the out of band and in band linearity requirements for both WCDMA and GGE modes","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132583297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A 18-GHz silicon bipolar VCO with transformer-based resonator 带变压器谐振器的18ghz硅双极压控振荡器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651186
A. Scuderi, E. Ragonese, T. Biondi, G. Palmisano
{"title":"A 18-GHz silicon bipolar VCO with transformer-based resonator","authors":"A. Scuderi, E. Ragonese, T. Biondi, G. Palmisano","doi":"10.1109/RFIC.2006.1651186","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651186","url":null,"abstract":"A silicon bipolar voltage-controlled oscillator for 17-GHz ISM band is presented. The VCO is composed of a core oscillating at 9 GHz followed by a frequency doubler. It adopts a transformer-based topology to obtain both wide tuning range and low noise performance. The VCO exhibits a tuning range of 4.1 GHz from 16.4 to 20.5 GHz and a phase noise as low as -109 dBc/Hz at a 1-MHz frequency offset from a carrier of 18.5 GHz. To design and optimize the resonator, a lumped scalable model for differentially driven inductors and transformers was used. This model is presented and validated up to 20 GHz by comparison with experimental data","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"5 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114058682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 5.8GHz, 47% efficiency, linear outphase power amplifier with fully integrated power combiner 一个5.8GHz, 47%效率，线性外相功率放大器与完全集成的功率合成器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651115
A. Pham, C. Sodini
{"title":"A 5.8GHz, 47% efficiency, linear outphase power amplifier with fully integrated power combiner","authors":"A. Pham, C. Sodini","doi":"10.1109/RFIC.2006.1651115","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651115","url":null,"abstract":"This paper presents an outphase power amplifier, consisting of two class-E power amplifiers and a power combiner. Using shielded coplanar striplines, the first low-loss, fully integrated 5.8 GHz Wilkinson combiner is realized with excellent isolation for a robust outphase PA. The outphase power amplifier, fabricated in IBM 7WL SiGe BiCMOS, achieves a peak efficiency of 47% at the maximum output power of 18.5dBm. For an orthogonal frequency division multiplexing input signal of 32 sub-channels of 64-QAM, the adjacent channel power leakage ratio is better than 32dBc","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121765750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Distributed amplifiers with non-uniform filtering structures 非均匀滤波结构的分布式放大器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651157
Yunliang Zhu, Hui Wu
{"title":"Distributed amplifiers with non-uniform filtering structures","authors":"Yunliang Zhu, Hui Wu","doi":"10.1109/RFIC.2006.1651157","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651157","url":null,"abstract":"This paper presents a new design concept to better control both passband and stop-band characteristics of distributed amplifiers (DAs) by using non-uniform filtering structures instead of conventional constant-k sections. Two circuit prototypes with Butterworth and Chebyshev filtering were designed using network synthesis method, and implemented in a 0.18mum digital CMOS technology. The Butterworth prototype achieved 11.7dB gain, 9GHz bandwidth, and -5dB/GHz roll-off. The Chebyshev one achieved 10dB gain, 8.5GHz bandwidth and -8dB/GHz roll-off","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126640050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A low-power FSK modulator using fractional-N synthesizer for wireless sensor network application 基于分数n合成器的低功耗FSK调制器，应用于无线传感器网络
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651121
D. Yan, T. Hui Teo, Bin Zhao, Y. Choi, W. Yeoh
{"title":"A low-power FSK modulator using fractional-N synthesizer for wireless sensor network application","authors":"D. Yan, T. Hui Teo, Bin Zhao, Y. Choi, W. Yeoh","doi":"10.1109/RFIC.2006.1651121","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651121","url":null,"abstract":"A low-power fractional-N synthesizer is designed for direct modulation transmitter at 2.40-2.50GHz range using standard 0.18mum CMOS. The synthesizer is fully implemented on-chip for integrated low data rate wireless sensor network (WSN) application. The data rate is as low as 10kbit/s. Phase noise of -93dBc/Hz at 600kHz offset is measured for the synthesizer. The active area is 0.8 times 0.8mm2, with total power of 8.0mW from a single 1.8V supply","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"72 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116658248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A double-balanced injection-locked frequency divider for tunable dual-phase signal generation 用于可调谐双相信号产生的双平衡注入锁定分频器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651105
Lin Zhang, Hui Wu
{"title":"A double-balanced injection-locked frequency divider for tunable dual-phase signal generation","authors":"Lin Zhang, Hui Wu","doi":"10.1109/RFIC.2006.1651105","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651105","url":null,"abstract":"We present an injection-locked divider (ILFD) with a double-balanced structure to generate two signals with tunable phase difference. A circuit prototype was designed and fabricated using a standard 0.18mum digital CMOS technology, and generates dual-phase signals at 4.8-6 GHz. The phase difference of the two output signals can be tuned independently by 55deg, and differentially by 100deg, both centered around quadrature (90deg). The phase noise degradation is negligible","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125998416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
High power LDMOS integrated Doherty amplifier for W-CDMA 用于W-CDMA的大功率LDMOS集成Doherty放大器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651183
I. Blednov, J. van der Zanden
{"title":"High power LDMOS integrated Doherty amplifier for W-CDMA","authors":"I. Blednov, J. van der Zanden","doi":"10.1109/RFIC.2006.1651183","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651183","url":null,"abstract":"To our knowledge a first integrated Doherty amplifier in a standard SOT502 package has been developed for WCDMA applications. This solution is based on 10W MMIC Doherty cell combined in parallel. The MMIC is based on the latest Philips LDMOST technology (Gen 6) and showed state of the art performance: 42% Eff has been measured at IMD3 level of -40dBc. Further improvement of linearity to below -50dBc was provided by digital pre-distortions. We believe this approach can be used to achieve powers above 120W. Moreover this approach will lead to a lower cost, more reliable and manufacturable Doherty product","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124389793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A low power low noise figure GPS/GALILEO front-end for handheld applications in a 0.35 /spl mu/m SiGe process 一款低功耗、低噪声的GPS/GALILEO前端，适用于手持应用，SiGe速率为0.35 /spl mu/m
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651077
R. Berenguer, J. Mendizabal, U. Alvarado, D. Valderas, A. Garcia-Alonso
{"title":"A low power low noise figure GPS/GALILEO front-end for handheld applications in a 0.35 /spl mu/m SiGe process","authors":"R. Berenguer, J. Mendizabal, U. Alvarado, D. Valderas, A. Garcia-Alonso","doi":"10.1109/RFIC.2006.1651077","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651077","url":null,"abstract":"A highly integrated, low power GALILEO/GPS front-end for the new generation of positioning services has been designed using a 0.35 mum SiGe process. It has been implemented using a 6 MHz bandwidth low IF architecture whose IF frequency is 4 MHz approximately. The front-end exhibits a voltage gain of 103 dB and present a SSB noise figure of 3.7 dB which makes it suitable for high sensitivity applications. The achieved power consumption is only 62 mW from a 3V voltage supply with no compromise with performance and with a minimal amount of external components","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133866064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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