{"title":"一个低噪声40-GS/s连续时间带通/spl Delta//spl Sigma/ ADC，中心为2GHz","authors":"T. Chalvatzis, S. Voinigescu","doi":"10.1109/RFIC.2006.1651147","DOIUrl":null,"url":null,"abstract":"A 2-GHz, continuous-time bandpass DeltaSigma analog-to-digital converter sampled with a 40-GHz clock was implemented in a 130-nm SiGe BiCMOS technology. It achieves an SNDR of 55 dB and 52 dB over 60 MHz and 120 MHz, respectively, and an SFDR of 61 dB with a single-ended IIP3 of +4 dBm. The center frequency is tunable from 1.8-2 GHz. It employs a Gm-LCVAR filter based on a MOS-HBT cascode transconductor with an NFmin of 2.3 dB. The ADC dissipates 1.6 W from a 2.5-V supply with a figure of merit of 18 pJ/sampled bit, including the contribution of the 40-GHz clock distribution network","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A low-noise 40-GS/s continuous-time bandpass /spl Delta//spl Sigma/ ADC centered at 2GHz\",\"authors\":\"T. Chalvatzis, S. Voinigescu\",\"doi\":\"10.1109/RFIC.2006.1651147\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 2-GHz, continuous-time bandpass DeltaSigma analog-to-digital converter sampled with a 40-GHz clock was implemented in a 130-nm SiGe BiCMOS technology. It achieves an SNDR of 55 dB and 52 dB over 60 MHz and 120 MHz, respectively, and an SFDR of 61 dB with a single-ended IIP3 of +4 dBm. The center frequency is tunable from 1.8-2 GHz. It employs a Gm-LCVAR filter based on a MOS-HBT cascode transconductor with an NFmin of 2.3 dB. The ADC dissipates 1.6 W from a 2.5-V supply with a figure of merit of 18 pJ/sampled bit, including the contribution of the 40-GHz clock distribution network\",\"PeriodicalId\":194071,\"journal\":{\"name\":\"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006\",\"volume\":\"54 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2006.1651147\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2006.1651147","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low-noise 40-GS/s continuous-time bandpass /spl Delta//spl Sigma/ ADC centered at 2GHz
A 2-GHz, continuous-time bandpass DeltaSigma analog-to-digital converter sampled with a 40-GHz clock was implemented in a 130-nm SiGe BiCMOS technology. It achieves an SNDR of 55 dB and 52 dB over 60 MHz and 120 MHz, respectively, and an SFDR of 61 dB with a single-ended IIP3 of +4 dBm. The center frequency is tunable from 1.8-2 GHz. It employs a Gm-LCVAR filter based on a MOS-HBT cascode transconductor with an NFmin of 2.3 dB. The ADC dissipates 1.6 W from a 2.5-V supply with a figure of merit of 18 pJ/sampled bit, including the contribution of the 40-GHz clock distribution network
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