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An area-efficient 5-GHz multiple receiver RFIC for MIMO WLAN applications 一种区域高效的5 ghz多接收机RFIC，用于MIMO WLAN应用
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651098
L. Khuon, S. Cg
{"title":"An area-efficient 5-GHz multiple receiver RFIC for MIMO WLAN applications","authors":"L. Khuon, S. Cg","doi":"10.1109/RFIC.2006.1651098","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651098","url":null,"abstract":"This paper presents area-efficient multiple receivers on a single-chip for 5-GHz MIMO wireless LAN systems. Each receiver has a low noise amplifier, Q-enhanced image reject filter, mixer, and local oscillator amplifier but shares a global local oscillator amplifier and distribution circuits for bias and filter tuning. The receivers are suitable for both spatial diversity and multiplexing. Area-efficiency results from frequency planning, circuit sharing, and application of spatial diversity. One receiver provides 14 dB gain, consumes 25 mA at 1.8 V, and occupies less than 1 mm chip area. The filter has better than 30 dB rejection at the image frequency","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127487739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An X-band SiGe LNA with 1.36 dB mean noise figure for monolithic phased array transmit/receive radar modules 用于单片相控阵收发雷达模块的平均噪声系数为1.36 dB的x波段SiGe LNA
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651200
W.-M.L. Kuo, Q. Liang, J. Cressler, M. Mitchell
{"title":"An X-band SiGe LNA with 1.36 dB mean noise figure for monolithic phased array transmit/receive radar modules","authors":"W.-M.L. Kuo, Q. Liang, J. Cressler, M. Mitchell","doi":"10.1109/RFIC.2006.1651200","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651200","url":null,"abstract":"This paper presents an X-band silicon-germanium (SiGe) low-noise amplifier (LNA) for a monolithically integrated phased array transmit/receive (T/R) radar module. Implemented in a 200 GHz SiGe BiCMOS technology, the LNA occupies 730 times 720 mum2 (including bondpads), and dissipates 15 mW from a 2.5 V power supply. The circuit exhibits a gain greater than 19 dB from 8.5 to 10.5 GHz, and a mean noise figure (NF) of 1.36 dB across X-band. At 10 GHz, the input 1-dB compression point (IP1-dB) and the input third-order intercept point (IIP3) are -10.0 dBm and 0.8 dBm, respectively. To our knowledge, this LNA achieves the lowest noise figure of any LNA in Si-based technology at X-band","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116879909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 65
Differential VCO and passive frequency doubler in 0.18 /spl mu/m CMOS for 24 GHz applications 差分压控振荡器和无源倍频器，0.18 /spl mu/m CMOS，适用于24 GHz应用
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651084
D. Ozis, N. Neihart, D. Allstot
{"title":"Differential VCO and passive frequency doubler in 0.18 /spl mu/m CMOS for 24 GHz applications","authors":"D. Ozis, N. Neihart, D. Allstot","doi":"10.1109/RFIC.2006.1651084","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651084","url":null,"abstract":"Circuits for generating a 24 GHz LO signal indirectly using a 12 GHz VCO cascaded with a 2times passive mixer and directly from a standalone 24 GHz VCO are compared. Both circuits are implemented in 0.18 mum CMOS. The 24 GHz designs exhibit equivalent phase noise, but the use of a passive mixer enables a 4times reduction in power consumption and a 2times increase in tuning range compared to the standalone 24 GHz VCO. The VCO/mixer combination shows phase noise of -99.94dBc/Hz @ 1 MHz offset from the 25.1 GHz carrier, 12% tuning range, and 11 mW of power consumption","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"492 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123058960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
A 0.18 /spl mu/m dual-gate CMOS model for the design of 2.4 GHz low noise amplifier 一种0.18 /spl mu/m双栅CMOS模型，用于设计2.4 GHz低噪声放大器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651154
K. Liang, Y. Chan
{"title":"A 0.18 /spl mu/m dual-gate CMOS model for the design of 2.4 GHz low noise amplifier","authors":"K. Liang, Y. Chan","doi":"10.1109/RFIC.2006.1651154","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651154","url":null,"abstract":"A dual-gate TSMC 0.18 mum gate-length n-MOS has been measured and characterized. The modified dual-gate large-signal model consists of two intrinsic, single-gate conventional BSIM3v3 nonlinear models and the passive network is proposed representing the device parasitic effects. This large-signal rf model includes the required passive components to fit the device dc and rf characteristics. The extrinsic elements of capacitance and inductance are calculated from the three-port S-parameters. Good agreement has been obtained between the simulation results of the equivalent circuit model and the measured data up to 15 GHz. In order to verify this modified model, a 2.4 GHz dual-gate low noise amplifier was designed based on this modified model. The LNA measurement results are consistent with the simulations, which demonstrate that the cascode-type dual-gate CMOS model can be applied for microwave circuit design","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123202949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 1 GHz /spl Sigma//spl Delta/ noise shaper for all digital PLLs with multiband UMTS modulation capability 1 GHz /spl Sigma//spl Delta/噪声整形器，适用于具有多频段UMTS调制能力的所有数字锁相环
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651189
T. Mayer, V. Neubauer, U. Vollenbruch, T. Pittorino, L. Maurer, A. Springer
{"title":"A 1 GHz /spl Sigma//spl Delta/ noise shaper for all digital PLLs with multiband UMTS modulation capability","authors":"T. Mayer, V. Neubauer, U. Vollenbruch, T. Pittorino, L. Maurer, A. Springer","doi":"10.1109/RFIC.2006.1651189","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651189","url":null,"abstract":"Fully digital phase locked loops (PLLs) for wideband phase modulation set tough requirements on the digitally controlled oscillator (DCO). The frequency step size should be small while the linear tuning range should be very large. To find a solution for both requirements, oversampling at the DCO can be applied. This relaxes the requirements for the oscillator, but needs additional high speed circuitry for realization. This paper describes the detailed requirements of an oversampling circuit for UMTS modulation. A noise shaping method is proposed, which enables the realization of a UMTS compliant DCO design. Furthermore, the implementation of an 8 bit 2nd order SigmaDelta-modulator in 0.13 mum CMOS is shown","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125292203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An analog correlator with dynamic bias control for pulse based UWB receiver in 0.18/spl mu/m CMOS technology 基于0.18/spl mu/m CMOS技术的脉冲超宽带接收机动态偏置控制模拟相关器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651145
D. Shen, F. Lin, W. Yeoh
{"title":"An analog correlator with dynamic bias control for pulse based UWB receiver in 0.18/spl mu/m CMOS technology","authors":"D. Shen, F. Lin, W. Yeoh","doi":"10.1109/RFIC.2006.1651145","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651145","url":null,"abstract":"This paper presents an analog correlator circuit for pulse-based ultra-wideband (UWB) communication. VGA-like architecture is chosen for the multiplier in the correlator. Dynamic bias control (DBC) is introduced. By controlling the multiplier only to work only when the local pulse is on, the contribution from the multiplier offset, integrator leakage and power consumption are all reduced. Analysis and measurement of this correlator are presented","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125364727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A dynamic supply CMOS RF power amplifier for 2.4GHz and 5.2GHz frequency bands 一种用于2.4GHz和5.2GHz频段的动态电源CMOS射频功率放大器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651112
P.A. Dal Fabbro, C. Meinen, M. Kayal, K. Kobayashi, Y. Watanabe
{"title":"A dynamic supply CMOS RF power amplifier for 2.4GHz and 5.2GHz frequency bands","authors":"P.A. Dal Fabbro, C. Meinen, M. Kayal, K. Kobayashi, Y. Watanabe","doi":"10.1109/RFIC.2006.1651112","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651112","url":null,"abstract":"An implementation of a dynamic supply RF power amplifier (PA) in 0.11mum CMOS technology occupying a total area of 1.35mm2 is presented. Two-tone measurement results at 2.4 and 5.2GHz show that the system can deliver over 16dBm linear output power with efficiencies of 22.7% and 12.6%, respectively. Compared to constant supply operation, besides providing higher linear output power, the dynamic supply technique allows over 230% relative efficiency enhancement at 2.4GHz and 160% at 5.2GHz at low output power levels. OFDM measurements at 2.4GHz demonstrated that at 3% error vector magnitude (EVM) the absolute improvement in efficiency is over 1.5%","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125215239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 0.18 /spl mu/m CMOS receiver for 3.1 to 10.6GHz MB-OFDM UWB communication systems 用于3.1至10.6GHz MB-OFDM UWB通信系统的0.18 /spl mu/m CMOS接收机
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651141
Yen-Horng Chen, Chih-Wei Wang, Ching-Feng Lee, Tzu-Yi Yang, Chih-Fan Liao, G. Ma, Shen-Iuan Liu
{"title":"A 0.18 /spl mu/m CMOS receiver for 3.1 to 10.6GHz MB-OFDM UWB communication systems","authors":"Yen-Horng Chen, Chih-Wei Wang, Ching-Feng Lee, Tzu-Yi Yang, Chih-Fan Liao, G. Ma, Shen-Iuan Liu","doi":"10.1109/RFIC.2006.1651141","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651141","url":null,"abstract":"A direct conversion receiver for MB-OFDM UWB communication systems operating in 3.1-10.6GHz is presented. It integrates a low noise amplifier (LNA), quadrature mixers, and baseband 6th-order channel-select filters with programmable gain. The receive chain provides conversion gain of 77dB with 58dB control range. The NF is about 5.8dB in 3-5GHz, rising to 7.6dB at 8GHz, and still below 9.3dB up to 10GHz. The IIP3 of -10.3dBm and IIP2 of 20.2dBm ensure a linear radio receiver. The circuit is fabricated in 0.18 mum CMOS process and mounted on a Rogers4003 PCB for measurement. It consumes 45mA and 38mA for LNA H/L gain mode from 1.8V supply","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127239056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Fully-integrated multi-standard VCOs with switched LC tank and power controlled by body voltage in 130nm CMOS/SOI 完全集成的多标准vco，具有开关LC油箱，功率由130nm CMOS/SOI体电压控制
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651103
L. Geynet, E. de Foucauld, P. Vincent, G. Jacquemod
{"title":"Fully-integrated multi-standard VCOs with switched LC tank and power controlled by body voltage in 130nm CMOS/SOI","authors":"L. Geynet, E. de Foucauld, P. Vincent, G. Jacquemod","doi":"10.1109/RFIC.2006.1651103","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651103","url":null,"abstract":"In this paper, the design of two VCOs for wireless multi-standard applications is presented. These circuits have been produced using CMOS/SOI technology, with body voltage to control power consumption and phase noise performance. A new architecture for multi-standard applications is proposed. To our knowledge, this is the first structure using a balun to change the oscillation frequency and the body biasing to control VCO core current. Four standards are covered by these structures: GSM (900MHz), DCS (1.8GHz), Bluetooth (2 GHz) and 802.11a (0.8GHz). The tuning range can vary from 80 MHz to 0.8GHz by using frequency divider, adjusted varactor and switched LC tank. The main idea is to use only two MOS varactors to cover the entire frequency span. The first one is needed to get the matched frequency variation and the second to adjust the oscillation frequency. Such VCOs can be made thanks to CMOS/SOI technology advantages, high-Q passives and body voltage biasing that allow current control and switched LC tank. At a frequency offset of 100kHz, the single side band phase noise measurements were -82dBc/Hz and -102dBc/Hz at 0.2GHz and 1.8GHz respectively","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127303067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 28 GHz sub-harmonic mixer using LO doubler in 0.18-/spl mu/m CMOS technology 采用0.18-/spl mu/m CMOS技术的LO倍频器的28 GHz次谐波混频器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651128
Tsung-Yu Yang, H. Chiou
{"title":"A 28 GHz sub-harmonic mixer using LO doubler in 0.18-/spl mu/m CMOS technology","authors":"Tsung-Yu Yang, H. Chiou","doi":"10.1109/RFIC.2006.1651128","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651128","url":null,"abstract":"A 28 GHz sub-harmonically pumped passive down conversion mixer fabricated in a 0.18-mum CMOS process is demonstrated. A low power fully differential LO frequency doubler is designed to generate at near half RF frequency. The proposed sub-harmonically pumped passive mixer has advantages in low power consumption, high fundamental frequency suppression, and suitable apply to millimeter-wave frequencies. At 28 GHz RF frequency and 13.2 GHz LO frequency, the measured conversion loss of the mixer is less than 11 dB, single side band noise figure of 11.6 dB, the isolations among LO, IF and RF are over 33 dB, and a third-order intercept point at the input of 8 dBm, while dissipating total current of 0.6 mA from 1 V supply. To the authors' knowledge, the design achieves the highest figure of merit among published down-conversion mixers operating at similar millimeter-wave frequencies in comparable silicon based technology","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"321 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133363077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
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