Jedon D. Kim, Hansu Oh, Chulho Chung, Joo-Hyun Jjeong, Hyunwoo Lee, S. Hwang, In-Chul Hwang, Young-jin Kim, K. Hong, E. Jung, K. Suh
{"title":"High performance NPN BJTs in standard CMOS process for GSM transceiver and DVB-H tuner","authors":"Jedon D. Kim, Hansu Oh, Chulho Chung, Joo-Hyun Jjeong, Hyunwoo Lee, S. Hwang, In-Chul Hwang, Young-jin Kim, K. Hong, E. Jung, K. Suh","doi":"10.1109/RFIC.2006.1651191","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651191","url":null,"abstract":"We report a high performance NPN bipolar junction transistor (BJT) processed in standard CMOS process that is applied to realize the direct conversion GSM receiver and DVB-H tuner. Through the variation of the base doping profile, performance of the NPN BJT has been tailored to meet the requirements of the RF circuits. Careful optimization is performed using both simulation and experiment. Optimized NPN BJT has maximum current gain of ~44, collector-emitter breakdown voltage of ~7V, collector-base breakdown voltage of ~20V, early voltage of ~25V, cutoff frequency of ~8.0GHz, and maximum oscillation frequency of ~11.6GHz. Low frequency noise characteristics of the NPN BJTs are investigated and the best structure for low noise level is identified. The corner frequency of the 1/f noise is ~2kHz at a collector current of ~1.7mA, which is ~4 orders lower than that of NMOS. As the flicker noise level is much lower than the CMOS, NPN BJT is used to realize the zero intermediate frequency (ZIF) direct conversion receiver (DCR) for GSM transceiver and DVB-H tuner. The resulting GSM receiver chain has a gain of over 50dB and noise figure of 2.5-3.0dB. For DVB-H tuner operating in the range of 470-850MHz, NF of 4.5dB and IIP3 of -5dBm are achieved at a gain of 64dB","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130057117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 40-Gb/s, digitally programmable peaking limiting amplifier with 20-dB differential gain in 90-nm CMOS","authors":"J. Weiss, M. Schmatz, H. Jaeckel","doi":"10.1109/RFIC.2006.1651163","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651163","url":null,"abstract":"A 40-Gb/s differential CMOS limiting amplifier in standard 90-nm technology is presented. The circuit dissipates as little as 80 mW from a 1 V power supply and has a differential gain of 20 dB. It can drive data at 40 Gb/s into multiple sampling circuits with a total input capacitance as high as 300 fF. The amplifier features a digitally programmable load resistor for the differential stages to control gain-peaking intensity. This can be used to cancel process variations or for active channel-compensation schemes. The output common mode voltage and circuit bias are controlled by a replica stage. The circuit occupies 0.033 mm2 of silicon real estate","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133369450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Mateo, J. Altet, E. Aldrete-Vidrio, J.L. Gonzalez
{"title":"Frequency characterization of a 2.4 GHz CMOS LNA by thermal measurements","authors":"D. Mateo, J. Altet, E. Aldrete-Vidrio, J.L. Gonzalez","doi":"10.1109/RFIC.2006.1651204","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651204","url":null,"abstract":"This paper presents a technique to obtain electrical characteristics of analog and RF circuits, based on measuring temperature at the silicon surface close to the circuit under test. Experimental results validate the feasibility of the technique. Simulated results show how this technique can be used to measure the bandwidth and central frequency of a 2.4 GHz low noise amplifier (LNA) designed in a 0.35 microns standard CMOS technology","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132699930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Ultra-low power RFIC design using moderately inverted MOSFETs: an analytical/experimental study","authors":"A. Shameli, P. Heydari","doi":"10.1109/RFIC.2006.1651193","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651193","url":null,"abstract":"This paper studies the use of moderately inverted MOS transistors in ultra-low power (ULP) RFIC design. We introduce a new figure of merit for a MOS transistor, i.e., the gmfT-to-current ratio, (gmfT/ID) which accounts for both the unity-gain frequency and current consumption during the optimization process of the transistor's performance. Using this figure of merit while taking into account the velocity saturation of short-channel MOS devices, it is shown both experimentally and analytically that the gmfT/ID reaches its maximum value in moderate inversion region. Moreover, we analytically investigate the noise behavior of the MOS transistor during the transition from weak inversion to strong inversion region. The measurement results have been obtained for an NMOS transistor fabricated in Jazz Semiconductor's CMOS process","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131882719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jeonghu Han, Younsuk Kim, Changkun Park, Dongho Lee, Songcheol Hong
{"title":"A fully-integrated 900-MHz CMOS power amplifier for mobile RFID reader applications","authors":"Jeonghu Han, Younsuk Kim, Changkun Park, Dongho Lee, Songcheol Hong","doi":"10.1109/RFIC.2006.1651174","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651174","url":null,"abstract":"A 900-MHz linear power amplifier has been fabricated for ultra-high-frequency (UHF) radio frequency identification (RFID) reader applications using a 0.25-mum CMOS technology. An on-chip transmission-line transformer is used for output matching network. Input and inter-stage matching components, and RF chokes are fully integrated in the designed amplifier so that no external components are required. The power amplifier provides linear output power of 27 dBm at 920 MHz with a 2.5-V supply. Power-added-efficiency (PAE) at 1-dB-gain-compression point (P1dB) is 28 %. Gain flatness over the full UHF RFID band, which covers from 860 MHz to 960 MHz, is 1 dB","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127392612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Integrated transformer baluns for RF low noise and power amplifiers","authors":"Haitao Gan, S. Wong","doi":"10.1109/RFIC.2006.1651093","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651093","url":null,"abstract":"On-chip transformer baluns integrated with an RF front-end architecture for medium power WLAN is presented. Method of measuring and characterizing a 3-port balun with a 2-port network analyzer is discussed. Implemented in 0.18mum CMOS, the receive path including a switch, an input transformer and a differential LNA, achieves S21 of 17dB, NF of 4.1dB, and IIP3 of 0dBm at 2.45GHz; the transmit path of a differential PA with an output transformer, achieves Psat of 21dBm, P1dB of 17dBm, and max PAE of 21%","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115193884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"AM-FM conversion by the active devices in MOS LC-VCOs and its effect on the optimal amplitude","authors":"B. Soltanian, P. Kinget","doi":"10.1109/RFIC.2006.1651102","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651102","url":null,"abstract":"Large oscillation amplitudes in differential MOS LC-VCOs change the operation region of the MOS negative-resistance devices and thus modulate their parasitic capacitances. As a result, the effective tank capacitance and the oscillation frequency change with respect to the oscillation amplitude for a fixed tuning voltage. The resulting frequency-versus-amplitude curve has a maximum for differential amplitude approximately equal to the threshold voltage of the MOS devices which corresponds to the optimum amplitude that minimizes AM-to-FM conversion. The presented analysis is confirmed with simulation and measurement results for a 2 GHz differential NMOS VCO fabricated in a 0.25 mum BiCMOS process. The optimum amplitude for lowest AM-to-FM conversion also yields the lowest phase noise for this oscillator","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114465310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Characterization of Si-based monolithic transformers with patterned ground shield","authors":"O. El-Gharniti, E. Kerhervé, J. Bégueret","doi":"10.1109/RFIC.2006.1651133","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651133","url":null,"abstract":"This paper investigates the impact of patterned ground shield on monolithic integrated transformers. The minimum insertion loss is shown to be a useful figure of merit. It is used to evaluate transformer performances. We demonstrate that the use of a patterned ground shield increases the quality factor of both primary and secondary coils. It increases also the mutual coupling coefficient and thus reduces the minimum insertion loss at high frequency, while at low frequency it has no effect. Measured insertion loss as low as 1.27dB at 5GHz, has been observed. The impact of patterned ground shield is shown to be more significant in the case of transformer with important transformation ratio","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123537995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Furukawa, Y. Hirano, T. Ohnakado, T. Ikeda, Y. Kagawa, K. Shintani, K. Nishikawa, S. Yamakawa, T. Ipposhi, S. Maegawa, M. Takeda, H. Arima
{"title":"RF components with high reliability and low loss by partial trench isolation of SOI-CMOS technology","authors":"A. Furukawa, Y. Hirano, T. Ohnakado, T. Ikeda, Y. Kagawa, K. Shintani, K. Nishikawa, S. Yamakawa, T. Ipposhi, S. Maegawa, M. Takeda, H. Arima","doi":"10.1109/RFIC.2006.1651094","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651094","url":null,"abstract":"This paper describes the experimental characteristics of RF components with layout and structural optimization, fabricated in 0.10-mum 1.2-V SOI-CMOS technology with partial trench isolation (PTI). ESD protection-grounded gate SOI-NMOSFETs achieve high reliability due to body-tied structure with PTI, and newly proposed ESD diodes also derive superior performance. Moreover, this technology offers a low loss RF switch and a broadband amplifier with low power consumption. These results are very promising for the fabrication of broadband RF integrated circuits","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"409 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122114455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evolution of a Software-Defined Radio Receiver's RF Front-End","authors":"A. Abidi","doi":"10.1109/RFIC.2006.1651080","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651080","url":null,"abstract":"The subject of this paper is how to construct this flexible receiver. We survey the steps that have been taken over the years in this direction - some very tenuously - leading up to a recent realization of a software-defined RF front-end. We do not cover the work that has gone into the digital front-end which follows the ADC (Hentschel and Fettweis, 2002), nor on the software-defined baseband - both are essential for a full radio. Furthermore, an efficient software-defined transmitter without which the software-defined radio project is incomplete is still in the research phase","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124462342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}