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2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)最新文献

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On the low frequency theory of characteristic mode 关于特征模态的低频理论
2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2015-12-07 DOI: 10.1109/EPEPS.2015.7347124
Q. Dai, W. Chew
{"title":"On the low frequency theory of characteristic mode","authors":"Q. Dai, W. Chew","doi":"10.1109/EPEPS.2015.7347124","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347124","url":null,"abstract":"We formulate a low frequency (LF) stabilized theory of characteristic mode (CM) to remedy LF breakdown and inaccuracy in computing dominant CMs, which are crucial for modal expansion and model order reduction in circuit applications.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126492978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application of CMA evolution strategy to synthesis of multi-resonance SPICE models up to 20 GHz CMA演化策略在20 GHz多共振SPICE模型合成中的应用
2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2015-12-07 DOI: 10.1109/EPEPS.2015.7347123
I. Kalimulin, A. Zabolotsky, T. Gazizov
{"title":"Application of CMA evolution strategy to synthesis of multi-resonance SPICE models up to 20 GHz","authors":"I. Kalimulin, A. Zabolotsky, T. Gazizov","doi":"10.1109/EPEPS.2015.7347123","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347123","url":null,"abstract":"A developed method for the macromodels synthesis in the form of an equivalent circuit consisting of RLC elements, using the active covariance matrix adaptation evolution strategy (active CMA-ES), is described. A fitness function taking into account the module and phase of the frequency dependence of reflection or transmission coefficient is described. Two examples of models synthesis for resistor and capacitor according to the measured frequency response, containing several resonances, are given. The developed models have shown good accuracy.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129752457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hierarchical modeling and scalable algorithms for in-situ analysis of integrated circuit packages 集成电路封装现场分析的分层建模和可扩展算法
2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2015-12-07 DOI: 10.1109/EPEPS.2015.7347125
Z. Peng, Yang Shao, Shu Wang
{"title":"Hierarchical modeling and scalable algorithms for in-situ analysis of integrated circuit packages","authors":"Z. Peng, Yang Shao, Shu Wang","doi":"10.1109/EPEPS.2015.7347125","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347125","url":null,"abstract":"The objective of this work is to investigate high-resolution and high-performance computational methods for the first-principles analysis of in-situ product-level integrated circuit (IC) packages. The novelties and key technical approaches of the proposed work include: (i) a scalable geometry-based domain decomposition (DD) method to conquer the geometric complexity of physical domain, which leads to quasi-optimal convergence that is provably scalable for multi-scale objects. Moreover, it results in parallel and scalable computational algorithms to reduce the time complexity via high performance computing facilities; (ii) a hierarchical multi-scale simulator for high-definition IC package systems, in which the technical ingredients include a skeleton-based multi-region multi-solver method and a variational macro-micro analysis for multi-scale modeling. The capability and benefits of the algorithms are explored and illustrated through several real-world 3D IC package applications.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131972210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
2D-FDFD with integrated via model for accurate simulation of PCBs and packages 2D-FDFD集成通孔模型，用于pcb和封装的精确仿真
2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2015-10-01 DOI: 10.1109/EPEPS.2015.7347144
S. Müller, M. Swaminathan
{"title":"2D-FDFD with integrated via model for accurate simulation of PCBs and packages","authors":"S. Müller, M. Swaminathan","doi":"10.1109/EPEPS.2015.7347144","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347144","url":null,"abstract":"This paper proposes a novel approach to directly integrate equivalent circuit models of vias in a 2D finite-differences frequency-domain method for the simulation of PCB and package structures. The via model serves two main purposes. First, it improves the accuracy of simulation results by modeling the modification of the local electric field in the vicinity of the via barrel. Second, it provides the coupling between different cavities, thus allowing to represent and solve a multilayer structure in a single 2D-FDFD system. In comparison to a related approach recently suggested in the literature, the procedure in this paper has two main advantages: First, it allows taking into account via barrel-to-plane capacitances at the proper positions in the equivalent circuit model, thus providing modeling accuracy. Second, its application to arbitrary numbers of cavities is straightforward. Both points are demonstrated with examples, showing good agreement to full-wave results up to 25 GHz.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124691811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The effect of temperature on performance of a RF CMOS power amplifer and bond wires 温度对射频CMOS功率放大器和键合线性能的影响
2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2015-10-01 DOI: 10.1109/EPEPS.2015.7347131
T. Kang, Donghwan Seo
{"title":"The effect of temperature on performance of a RF CMOS power amplifer and bond wires","authors":"T. Kang, Donghwan Seo","doi":"10.1109/EPEPS.2015.7347131","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347131","url":null,"abstract":"In this work, low and high temperature environmental tests were conducted on a switching mode RF CMOS power amplifier according to the MIL-STD-810G standard. The efficiency of the power amplifier was increased by 5% at −32 °C while it was decreased by 4% at 63 °C. In order to determine the influence of interconnects on the performance, the effect of temperature on single bond wires of different lengths was investigated. In results, the S21 parameter (dB) of the bond wires showed a linear and inverse relationship with varying temperature. Compared with the S21 parameter obtained at the standard ambient condition, it was varied by ±7.5 % in the temperature range from −60 °C to 120 °C, which cannot be neglected. Furthermore, it is shown that the electrical loss of interconnects increases with rising temperature because of the thermal expansion and increase in the resistivity.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115106876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Return loss characterization and analysis of high-speed serial interface 高速串行接口回波损耗特性与分析
2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 2015-10-01 DOI: 10.1109/EPEPS.2015.7347162
W. Beyene, C. Madden, N. Vaidya
{"title":"Return loss characterization and analysis of high-speed serial interface","authors":"W. Beyene, C. Madden, N. Vaidya","doi":"10.1109/EPEPS.2015.7347162","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347162","url":null,"abstract":"This paper described the return loss characterization and analysis of a high-speed serial interface with T-coils at the transmitter and receiver. Today's high-speed links utilize equalization to mitigate channel loss and dispersion. In addition, T-coil networks are used at inputs and outputs to improve impedance matching and to enhance the receiver and transmitter bandwidth. To guarantee the transceiver performance, a wide range of Serializer Deserializer (SerDes) compliance specifications exist for the return loss measured at or near the package interface and the Printed Circuit Board (PCB). For multi-protocol SerDes, thus, T-coil networks are often necessary to meet the most stringent return loss specification. This paper presents the analysis and characterization of a high-speed transceiver with T-coils designed in a 28 nm CMOS process. Measurements are also presented to demonstrate the improvement in return loss and bandwidth of the transceiver.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132364568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Fabrication challenge, device characterization of high-Q 2D, 3D passives devices on glass 玻璃上高q 2D, 3D无源器件的制造挑战，器件特性
2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 1900-01-01 DOI: 10.1109/EDAPS.2016.7893130
Sheng-Chi Hsieh, Chien-Hua Chen, Yung-shun Chang, T. Lee, Pao-Nan Lee, Chen-Chao Wang, Yuan-Hsi Chou
{"title":"Fabrication challenge, device characterization of high-Q 2D, 3D passives devices on glass","authors":"Sheng-Chi Hsieh, Chien-Hua Chen, Yung-shun Chang, T. Lee, Pao-Nan Lee, Chen-Chao Wang, Yuan-Hsi Chou","doi":"10.1109/EDAPS.2016.7893130","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893130","url":null,"abstract":"It is demonstrated that the high quality factor of thick metal spiral inductors, 3D solenoid inductor and low harmonics power level can be achieved by using a mature glass substrate technology. The quality factor of inductors in a 2D/3D type can achieve 70∼100 in this study. The harmonics power level is measured along transmission line and 2nd /3rd harmonics can be below −110 dBm at 30 dBm input power. It is very critical and helpful with high Q-factor and lower harmonics power level for the FEM development of current and next generation's commercial 4G carrier aggregation system.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"20 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120972501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Parameterize via structure to resolve high speed discontinuity in PCIe 5 GT/s 通过结构参数化来解决PCIe 5gt /s高速不连续问题
2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 1900-01-01 DOI: 10.1109/EDAPS.2016.7893139
Chua Fu Lien, Koh Wee Jin
{"title":"Parameterize via structure to resolve high speed discontinuity in PCIe 5 GT/s","authors":"Chua Fu Lien, Koh Wee Jin","doi":"10.1109/EDAPS.2016.7893139","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893139","url":null,"abstract":"Via structure can be parameterized into model consisting of lump components. This model can be used for resolving SI issues such as discontinuities on PCIe high speed channel. In this paper, the proposed approach on parameterizing the via has improved the performance of PCIe 5 GT/s channels, consisting of unavoidable VPX connector via stubs, and also hasten the simulation time to resolve via discontinuity.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128175165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fast thermal simulation of integrated systems using alternating-direction-implicit method 交替方向隐式集成系统快速热模拟
2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 1900-01-01 DOI: 10.1109/EDAPS.2016.7893165
Qiangqiang Feng, M. Tang, Guangcao Fu, Junfa Mao
{"title":"Fast thermal simulation of integrated systems using alternating-direction-implicit method","authors":"Qiangqiang Feng, M. Tang, Guangcao Fu, Junfa Mao","doi":"10.1109/EDAPS.2016.7893165","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893165","url":null,"abstract":"An efficient transient thermal simulation of complex integrated system is carried out based on the equivalent thermal model and alternating-direction-implicit (ADI) method. The temperature-dependent leakage power dissipation in chips is taken into account in the modeling. With the ADI technique, the heat conduction equations in the matrix form are solved with linear computational complexity and memory requirement. The validity and high-efficiency of the proposed method are demonstrated by the numerical examples.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134151894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Efficient time-domain variability analysis of active circuits 有源电路的有效时域变异性分析
2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Pub Date : 1900-01-01 DOI: 10.1109/EDAPS.2016.7893162
K. Guo, F. A. Sheikh, B. Nouri, F. Ferranti, M. Nakhla
{"title":"Efficient time-domain variability analysis of active circuits","authors":"K. Guo, F. A. Sheikh, B. Nouri, F. Ferranti, M. Nakhla","doi":"10.1109/EDAPS.2016.7893162","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893162","url":null,"abstract":"An advanced technique for numerical inversion of Laplace transform is presented for time-domain statistical analysis of large active circuits with multiple stochastic parameters. The proposed method is based on a model-order reduction technique that guarantees the stability of the reduced active circuit by construction. Pertinent numerical results are presented that validate the efficiency and accuracy of the proposed method.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115622990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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