{"title":"通过结构参数化来解决PCIe 5gt /s高速不连续问题","authors":"Chua Fu Lien, Koh Wee Jin","doi":"10.1109/EDAPS.2016.7893139","DOIUrl":null,"url":null,"abstract":"Via structure can be parameterized into model consisting of lump components. This model can be used for resolving SI issues such as discontinuities on PCIe high speed channel. In this paper, the proposed approach on parameterizing the via has improved the performance of PCIe 5 GT/s channels, consisting of unavoidable VPX connector via stubs, and also hasten the simulation time to resolve via discontinuity.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Parameterize via structure to resolve high speed discontinuity in PCIe 5 GT/s\",\"authors\":\"Chua Fu Lien, Koh Wee Jin\",\"doi\":\"10.1109/EDAPS.2016.7893139\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Via structure can be parameterized into model consisting of lump components. This model can be used for resolving SI issues such as discontinuities on PCIe high speed channel. In this paper, the proposed approach on parameterizing the via has improved the performance of PCIe 5 GT/s channels, consisting of unavoidable VPX connector via stubs, and also hasten the simulation time to resolve via discontinuity.\",\"PeriodicalId\":191549,\"journal\":{\"name\":\"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAPS.2016.7893139\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAPS.2016.7893139","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Parameterize via structure to resolve high speed discontinuity in PCIe 5 GT/s
Via structure can be parameterized into model consisting of lump components. This model can be used for resolving SI issues such as discontinuities on PCIe high speed channel. In this paper, the proposed approach on parameterizing the via has improved the performance of PCIe 5 GT/s channels, consisting of unavoidable VPX connector via stubs, and also hasten the simulation time to resolve via discontinuity.