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2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)最新文献

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Optimization of 65nm CMOS passive devices to design a 16 dBm-Psat 60 GHz power amplifier 优化65nm CMOS无源器件，设计16dbm - psat 60ghz功率放大器
2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519034
S. Aloui, B. Leite, N. Demirel, R. Plana, D. Belot, E. Kerhervé
{"title":"Optimization of 65nm CMOS passive devices to design a 16 dBm-Psat 60 GHz power amplifier","authors":"S. Aloui, B. Leite, N. Demirel, R. Plana, D. Belot, E. Kerhervé","doi":"10.1109/LASCAS.2013.6519034","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6519034","url":null,"abstract":"The optimization of passive devices is performed to contribute to the design of a linear 60 GHz Power Amplifier (PA). The difficulty in this design consists in the use of thin digital 7 metal layers (1P7M) Back End of Line (BEOL) and Low Power (LP) transistors dedicated for pure digital applications. In this context, compact inductors and Transmission lines (T-lines) are analyzed, measured and compared at millimeter-Wave (mmW) frequencies. Moreover, a technique of Common Mode Rejection Ration (CMRR) improvement applied for baluns is presented and validated with measurements. A Parallel PA that combines 8 high-efficiency unit power cells is designed using 65nm CMOS technology from STMicroelectronics. The experimental results show a saturated output power (Psat) of 16 dBm with a 14 dBm 1dB-output compression point (OCP1dB).","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121180877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A strategy for mapping reconfigurable cores in NoCs 一种在noc中映射可重构核心的策略
2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519003
Jonas Gomes Filho, M. Strum, W. Chau
{"title":"A strategy for mapping reconfigurable cores in NoCs","authors":"Jonas Gomes Filho, M. Strum, W. Chau","doi":"10.1109/LASCAS.2013.6519003","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6519003","url":null,"abstract":"In the last years, Field programmable gate-arrays (FPGAs) with partial reconfiguration capabilities have raised interest in the implementation of dynamically reconfigurable systems (DSRs). For dealing with the issue of communication between reconfigurable and fixed partitions, Networks-on-Chip (NoCs) have gained importance in DSR architectures. The mapping of cores in NoCs aims to find the best topological location onto the NoC, such that the metrics of interest can be greatly optimized. In this paper, the mapping strategy for reconfigurable cores into NoCs is presented and the sensibility in respect to the cost function is evaluated. Results confirm the need for mapping optimization algorithms aimed to reduce both the traffic and power consumption.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124073002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of an elliptic curve cryptoprocessor using optimal normal basis over GF(2233) GF(2233)上最优正规基椭圆曲线密码处理器的设计
2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519014
F. A. Urbano-Molano, V. Trujillo-Olaya, Jaime Velasco-Medina
{"title":"Design of an elliptic curve cryptoprocessor using optimal normal basis over GF(2233)","authors":"F. A. Urbano-Molano, V. Trujillo-Olaya, Jaime Velasco-Medina","doi":"10.1109/LASCAS.2013.6519014","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6519014","url":null,"abstract":"This paper presents the design of an elliptic curve cryptoprocessor using optimal normal basis. The scalar point multiplication is implemented using random curves over GF(2233), and the finite field multiplication is implemented using bit-serial and parallel multiplication algorithms. The designed processor is flexible, parameterized and described by using VHDL. This allows achieving a good trade-off between area, performance and flexibility. The execution times to carry out the scalar point multiplication of the designed cryptoprocessor using bit-serial and parallel multiplication were 1.62 μs and 0.025 μs, respectively. The performance results show that this cryptoprocessor can be used as a hardware coprocessor for high performance reconfigurable cryptosystems.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126364019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Hardware realization of a lightweight 2D cellular automata-based cipher for image encryption 一种轻量级二维元胞自动机图像加密算法的硬件实现
2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519023
C. Torres-Huitzil
{"title":"Hardware realization of a lightweight 2D cellular automata-based cipher for image encryption","authors":"C. Torres-Huitzil","doi":"10.1109/LASCAS.2013.6519023","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6519023","url":null,"abstract":"Cryptography is one of the fundamental techniques used to secure data storage and transmission of sensitive multimedia data exchanged between different communicating parties. Several mobile and embedded devices are equipped with high resolution digital cameras and resources for multimedia management but most of them lack mechanisms to protect image content due to the additional computational cost of cryptographic algorithms and the inherent power constraints in such resource-limited devices. In this paper, a two-dimensional (2D) cellular automata (CA) based stream cipher for color image encryption is presented. A CA is used to generate a good quality pseudorandom bit sequence that is used in a stream cipher scheme for color image encryption that outperforms related works. The proposed scheme, prototyped into a field-programmable gate array (FPGA) device, allows image encryption with reduced hardware resource utilization suitable to be embedded as a low-power component in mobile computing systems.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130615804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Fully integrated single-inductor multiple-output (SIMO) DC-DC converter in CMOS 65 nm technology 完全集成的单电感多输出(SIMO) DC-DC转换器在CMOS 65纳米技术
2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519071
A. J. Soto, E. Lindstrom, A. Oliva, P. Mandolesi, F. Dualibe
{"title":"Fully integrated single-inductor multiple-output (SIMO) DC-DC converter in CMOS 65 nm technology","authors":"A. J. Soto, E. Lindstrom, A. Oliva, P. Mandolesi, F. Dualibe","doi":"10.1109/LASCAS.2013.6519071","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6519071","url":null,"abstract":"In the nanoscale technologies, the on-chip Power Management design strategy as a part of a System on Chip (SoC) is becoming extremely important. This work presents a fully integrated SIMO converter in a CMOS 65 nm technology. Since passive components are also integrated and their values should result relatively small the converter operates at a switching frequency of 200 MHz. This version counts with a step-up and a step-down outputs, but it can be easily extended to more otuputs. A suitable control strategy for high speed and nano-scale process together with system simulation results are discused.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134135898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Long range dependence in intrachip transaction level traffic 芯片内事务级流量的长距离依赖
2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519074
Jorge González, G. Alvarez, M. Strum, W. Chau
{"title":"Long range dependence in intrachip transaction level traffic","authors":"Jorge González, G. Alvarez, M. Strum, W. Chau","doi":"10.1109/LASCAS.2013.6519074","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6519074","url":null,"abstract":"This work1 presents the statistical evaluation over traffic traces from multimedia applications executed on both Cycle Accurate Level and Transaction Level Platforms. We performed the statistical analysis over the captured traffic to determine if relevant characteristics such as impulsivity and LRD could be maintained on traffic obtained by simulation on higher level abstraction description models. Our experiments show that the transaction level traffic exhibits similar statistical behaviour as the cycle accurate traffic and could be used to generate synthetic traffic series for Network-on-chip simulation.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129121645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analog circuits for modeling and controlling synchrony in arrays of coupled oscillators 耦合振荡器阵列同步建模与控制的模拟电路
2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6518977
A. Petrovas, E. Tamaseviciute, G. Mykolaitis, A. Tamasevicius, R. Stoop
{"title":"Analog circuits for modeling and controlling synchrony in arrays of coupled oscillators","authors":"A. Petrovas, E. Tamaseviciute, G. Mykolaitis, A. Tamasevicius, R. Stoop","doi":"10.1109/LASCAS.2013.6518977","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6518977","url":null,"abstract":"An analog technique for desynchronisation of FitzHugh-Nagumo type oscillators is described. Two-terminal feedback controller is applied to the network. The controller nullifies the voltage at the coupling node and effectively decouples the individual oscillators. Both, numerical simulations and hardware experiments are performed. The results for array of 30 coupled FitzHugh-Nagumo oscillators are presented.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127589913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reducing the Hamming distance of encoded FFT twiddle factors using improved heuristic algorithms 利用改进的启发式算法减小编码FFT旋转因子的汉明距离
2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519053
A. Luz, E. Costa, S. Ghissoni
{"title":"Reducing the Hamming distance of encoded FFT twiddle factors using improved heuristic algorithms","authors":"A. Luz, E. Costa, S. Ghissoni","doi":"10.1109/LASCAS.2013.6519053","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6519053","url":null,"abstract":"This paper addresses the exploration of different heuristic algorithms for a better manipulation of twiddle factors of Fast Fourier Transform (FFT). The FFT algorithm involve multiplications of input data with appropriate coefficients, hence the best ordering of those operations can contribute for reducing the switching activity, what leads to the minimization of power consumption in FFTs. The heuristic algorithm named Bellmore and Nemhauser, and a proposed one named Anedma in both original and improved versions, are used to get as near as possible to the optimal solution for the ordering and partitioning of coefficients in FFTs. Data encoding methods are used for decreasing switching activity for transmitting information over buses, hence we have used some encoding techniques in the coefficients. As will be shown, the appropriate ordering of coefficients, based on the guidance given by the improved Anedma algorithm, can contribute for the reduction of Hamming distance of the encoded twiddle factors.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124823790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Efficient parallel scheduler for circuit simulation exploiting binary link formulations 利用二进制链路公式进行电路仿真的高效并行调度程序
2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519091
D. Paul, R. Achar, M. Nakhla, N. Nakhla
{"title":"Efficient parallel scheduler for circuit simulation exploiting binary link formulations","authors":"D. Paul, R. Achar, M. Nakhla, N. Nakhla","doi":"10.1109/LASCAS.2013.6519091","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6519091","url":null,"abstract":"As circuit sizes increase, a means to improve the performance of simulations is constantly demanded, without sacrificing the accuracy of the results. To achieve this goal, a new parallel scheduler is presented exploiting binary link formulations that allows modern multi-core processors to achieve superior performance. These improvements are obtained without sacrificing accuracy or resorting to iterative techniques.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124246118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low-power, offset-corrected potentiostat for chemical imaging applications 一种用于化学成像应用的低功率、偏移校正的恒电位器
2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519041
Kern Tucker, Tom Chen
{"title":"A low-power, offset-corrected potentiostat for chemical imaging applications","authors":"Kern Tucker, Tom Chen","doi":"10.1109/LASCAS.2013.6519041","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6519041","url":null,"abstract":"Traditional potentiostat designs often focus on high accuracy using high precision discrete components and often involve a limited number of discrete electrodes. Modern medicine and biological research require the use of high-density biosensor arrays to gain a better understanding of cellular communication in biological systems. Such applications involves hundreds or thousands of electrodes on a single silicon substrate. Each set of electrodes is supported by an independent group of circuits to allow real-time, multichannel detection and characterization of bio-signals. This paper presents a low power, offset-calibrated potentiostat design in a commercial 0.18um CMOS process for use in single-chip biosensor array applications to generate high resolution chemical images. The design uses a reusable on-chip calibration circuit to reduce amplifier offset error, with 40.3 μW of power consumption and a total silicon area of .02 mm2.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123417392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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