S. Aloui, B. Leite, N. Demirel, R. Plana, D. Belot, E. Kerhervé
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Optimization of 65nm CMOS passive devices to design a 16 dBm-Psat 60 GHz power amplifier
The optimization of passive devices is performed to contribute to the design of a linear 60 GHz Power Amplifier (PA). The difficulty in this design consists in the use of thin digital 7 metal layers (1P7M) Back End of Line (BEOL) and Low Power (LP) transistors dedicated for pure digital applications. In this context, compact inductors and Transmission lines (T-lines) are analyzed, measured and compared at millimeter-Wave (mmW) frequencies. Moreover, a technique of Common Mode Rejection Ration (CMRR) improvement applied for baluns is presented and validated with measurements. A Parallel PA that combines 8 high-efficiency unit power cells is designed using 65nm CMOS technology from STMicroelectronics. The experimental results show a saturated output power (Psat) of 16 dBm with a 14 dBm 1dB-output compression point (OCP1dB).
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